M48Z58Y-70PC1 STMicroelectronics, M48Z58Y-70PC1 Datasheet - Page 8

• Manufacturer Part Number: M48Z58Y-70PC1
• Description: IC NVSRAM 64KBIT 70NS 28DIP
• Manufacturer: STMicroelectronics

Specifications of M48Z58Y-70PC1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 64K (8K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Data Bus Width: 8 bit
• Organization: 8 Kb x 8
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Operating Current: 50 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3685-5

Operating modes
2
Note:
2.1
8/24
Operating modes
The M48Z58/Y also has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
switchover voltage (V
until valid power returns.
Table 2.
1. See
X = V
READ mode
The M48Z58/Y is in the READ mode whenever W (WRITE enable) is high, E (chip enable) is
low. Thus, the unique address specified by the 13 address inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within
address access time (t
and G access times are also satisfied. If the E and G access times are not met, valid data
will be available after the latter of the chip enable access time (t
access time (t
The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are
activated before t
the address inputs are changed while E and G remain active, output data will remain valid
for output data hold time (t
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
IH
Table 10 on page 16
or V
IL
V
Operating modes
; V
SO
GLQV
4.75 to 5.5 V
4.5 to 5.5 V
SO
to V
AVQV
≤ V
).
V
= Battery backup switchover voltage.
PFD
or
SO
CC
SO
, the data lines will be driven to an indeterminate state until t
AVQV
(1)
), the control circuitry connects the battery which maintains data
for details.
(min)
AXQX
) after the last address input signal is stable, providing that the E
(1)
Doc ID 2559 Rev 10
) but will go indeterminate until the next address access.
V
V
V
V
E
X
X
IH
IL
IL
IL
V
V
G
X
X
X
X
IH
IL
V
V
V
W
X
X
X
IH
IH
IL
DQ0-DQ7
High Z
High Z
High Z
High Z
D
D
OUT
IN
CC
. As V
ELQV
) or output enable
Battery backup mode
CC
CC
CMOS standby
M48Z58, M48Z58Y
falls below battery
Standby
is out of
Power
Active
Active
Active
AVQV
. If