CY7C1393CV18-250BZXC Cypress Semiconductor Corp, CY7C1393CV18-250BZXC Datasheet
CY7C1393CV18-250BZXC
Specifications of CY7C1393CV18-250BZXC
Available stocks
Related parts for CY7C1393CV18-250BZXC
CY7C1393CV18-250BZXC Summary of contents
Page 1
... K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and two 36-bit words in the case of CY7C1394CV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the ...
Page 2
... Address A (19:0) Register K CLK K Gen. DOFF R/W V REF Control Logic LD BWS [0] Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Write Write Data Reg Data Reg Control Logic Read Data Reg Reg. Reg. 8 Reg. Write Write Data Reg Data Reg Control Logic Read Data Reg. ...
Page 3
... Logic Block Diagram (CY7C1393CV18 [17:0] 19 Address A (18:0) Register K CLK K Gen. DOFF R/W V REF Control Logic LD BWS [1:0] Logic Block Diagram (CY7C1394CV18 [35:0] 18 Address A (17:0) Register K CLK K Gen. DOFF R/W V REF Control Logic LD BWS [3:0] Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 ...
Page 4
... Pin Configuration The Pin Configuration for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows NC/72M DOFF V V REF DDQ TDO TCK NC/72M DOFF V V REF DDQ TDO TCK A Note 1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level. ...
Page 5
... Pin Configuration (continued) The Pin Configuration for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows NC/144M NC/36M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO ...
Page 6
... Synchronous arrays each for CY7C1392CV18 arrays each for CY7C1992CV18 arrays each of 512K x 18) for CY7C1393CV18 and 512K arrays each of 256K x 36) for CY7C1394CV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1392CV18 and CY7C1992CV18, 19 address inputs for CY7C1393CV18 and 18 address inputs for CY7C1394CV18 ...
Page 7
... Ground Ground for the device Power Supply Power supply inputs for the outputs of the device. DDQ Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Pin Description Switching Characteristics on page 23. Switching Characteristics on page 23. output impedance are set to 0.2 x RQ, where resistor [x:0] , which ...
Page 8
... This feature can be used to simplify read/modify/write operations to a byte write operation. Single Clock Mode The CY7C1393CV18 can be used with a single clock that controls both the input and output registers. In this mode the ) inputs pass through device recognizes only a single pair of input clocks (K and K) that control both the input and output registers ...
Page 9
... 50Ohms Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However not necessary to reset the DLL to lock it to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented ...
Page 10
... Truth Table The truth table for CY7C1392CV18, CY7C1992CV18, CY7C1393CV18, and CY7C1394CV18 follows. Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges. ...
Page 11
... L– – Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 [2, 8] Comments [ Comments – During the data portion of a write sequence, all four bytes (D the device. L–H During the data portion of a write sequence, all four bytes (D the device. – During the data portion of a write sequence, only the lower byte (D into the device ...
Page 12
... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 15 ...
Page 13
... Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins ...
Page 14
... The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1-DR ...
Page 15
... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 11. Overshoot: V (AC) < 0.85V (Pulse width less than t IH DDQ 12. All Voltage referenced to Ground. Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 0 Bypass Register Instruction Register ...
Page 16
... CS CH 14. Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Description [14] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50Ω ...
Page 17
... RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Value CY7C1992CV18 CY7C1393CV18 000 000 00000110100 00000110100 1 ...
Page 18
... Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 1H 10D 10C 66 3B 11D 11B ...
Page 19
... DDQ DOFF Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as t ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior ...
Page 20
... V REF DDQ 19. The operation current is calculated with 50% read cycle and 50% write cycle. Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch-up Current ................................................... > 200 mA Operating Range Range Commercial ...
Page 21
... I Automatic Power Down SB1 Current AC Electrical Characteristics [11] Over the Operating Range Parameter Description V Input HIGH Voltage IH V Input LOW Voltage IL Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Test Conditions V = Max, 200 MHz (x8 mA, OUT (x9 1/t MAX CYC (x18) (x36) 167 MHz ...
Page 22
... Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V 250Ω, V pulse levels of 0.25V to 1.25V, and output loading of the specified I Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Test Conditions T = 25° MHz 1.8V, V ...
Page 23
... This part has a voltage regulator internally; t POWER initiated. 23. For D2 data signal on CY7C1992CV18 device, t Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max [22 ...
Page 24
... CHZ CLZ 26. At any voltage and temperature t is less than t CHZ Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 300 MHz 278 MHz Min Max Min Max Min Max Min Max Min Max – 0.45 – 0.45 – ...
Page 25
... Outputs are disabled (High-Z) one clock cycle after a NOP. 29. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 READ WRITE WRITE ...
Page 26
... CY7C1392CV18-278BZXI CY7C1992CV18-278BZXI CY7C1393CV18-278BZXI CY7C1394CV18-278BZXI Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( ...
Page 27
... Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code 250 CY7C1392CV18-250BZC CY7C1992CV18-250BZC CY7C1393CV18-250BZC CY7C1394CV18-250BZC CY7C1392CV18-250BZXC CY7C1992CV18-250BZXC CY7C1393CV18-250BZXC CY7C1394CV18-250BZXC CY7C1392CV18-250BZI CY7C1992CV18-250BZI CY7C1393CV18-250BZI CY7C1394CV18-250BZI CY7C1392CV18-250BZXI CY7C1992CV18-250BZXI CY7C1393CV18-250BZXI CY7C1394CV18-250BZXI 200 CY7C1392CV18-200BZC CY7C1992CV18-200BZC CY7C1393CV18-200BZC ...
Page 28
... CY7C1392CV18-167BZXI CY7C1992CV18-167BZXI CY7C1393CV18-167BZXI CY7C1394CV18-167BZXI Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( ...
Page 29
... Package Diagram Figure 6. 165-Ball FBGA ( 1.4 mm), 51-85180 TOP VIEW PIN 1 CORNER 13.00±0.10 SEATING PLANE C Document #: 001-07162 Rev. *C CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 0.15(4X) BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. -0.06 Ø0.50 (165X) +0. 1.00 5.00 10.00 13.00±0.10 NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0 ...
Page 30
... Document History Page Document Title: CY7C1392CV18/CY7C1992CV18/CY7C1393CV18/CY7C1394CV18, 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number: 001-07162 Submission Orig. of Rev. ECN No. Date Change ** 433284 See ECN NXR *A 462615 See ECN NXR *B 1523386 See ECN VKN/AESA Converted from preliminary to final, Updated Logic Block diagram, Updated I ...