CY7C1480BV33-167AXC Cypress Semiconductor Corp, CY7C1480BV33-167AXC Datasheet - Page 7

• Manufacturer Part Number: CY7C1480BV33-167AXC
• Description: IC SRAM 72MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480BV33-167AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Document #: 001-15145 Rev. *A
Note
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQs, DQPs
V
V
V
V
1. Applicable for TQFP package. For BGA package V
Pin Name
0
DD
SS
SSQ
DDQ
, A
1
2
3
A
E
,BW
,BW
1
[1]
, A
B
F
,BW
,BW
G
C
,BW
,BW
H
D
,
IO Power Supply Power supply for the IO circuitry.
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
IO Ground
Ground
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
IO-
IO
Address Inputs used to Select One of the Address Locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE
sampled active. A1: A0 are fed to the 2-bit counter.
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (all bytes are written, regardless of the values on
BW
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW during a burst operation.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
is HIGH. CE
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
when a new external address is loaded.
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
when a new external address is loaded.
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO
pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read
cycle when emerging from a deselected state.
Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When
asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
deasserted HIGH.
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin must be LOW or left floating. ZZ pin has an internal pull down.
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise
of the read cycle. The direction of the pins is controlled by OE. When OE is asserted
LOW, the pins behave as outputs. When HIGH, DQs and DQP
condition.
Power Supply Inputs to the Core of the Device.
Ground for the Core of the Device.
Ground for the IO Circuitry.
SS
X
serves as ground for the core and the IO circuitry.
and BWE).
1
is sampled only when a new external address is loaded.
2
1
1
and CE
and CE
and CE
3
2
3
to select or deselect the device. ADSP is ignored if CE
to select or deselect the device. CE
to select or deselect the device. CE
CY7C1482BV33, CY7C1486BV33
Description
X
are placed in a tri-state
CY7C1480BV33
1
, CE
3
2
is sampled only
is sampled only
2
, and CE
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3
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