CY7C1518AV18-250BZXI Cypress Semiconductor Corp, CY7C1518AV18-250BZXI Datasheet - Page 23

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CY7C1518AV18-250BZXI

Manufacturer Part Number
CY7C1518AV18-250BZXI
Description
IC SRAM 72MBIT 250MHZ 165TFBGA
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1518AV18-250BZXI

Format - Memory
RAM
Memory Type
SRAM - Synchronous, DDR II
Memory Size
72M (4M x 18)
Speed
250MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1518AV18-250BZXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-06982 Rev. *F
Parameter
Output Times
t
t
t
t
t
t
t
t
t
t
DLL Timing
t
t
t
CO
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ
CLZ
KC Var
KC lock
KC Reset
23. These parameters are extrapolated from the input timing parameters (t
24. t
25. At any voltage and temperature t
Cypress
included in the t
CHZ
, t
CLZ
are specified with a load capacitance of 5 pF as in (b) of
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
CHQX1
KC Var
KC lock
KC Reset
Parameter
KHKH
). These parameters are only guaranteed by design and are not tested in production.
C/C clock rise (or K/K in single clock
mode) to data valid
Data output hold after output C/C
clock rise (active to active)
C/C clock rise to echo clock valid
Echo clock hold after C/C clock rise –0.45
Echo clock high to data valid
Echo clock high to data invalid
Output clock (CQ/CQ) high
CQ clock rise to CQ clock rise (rising
edge to rising edge)
Clock (C/C) rise to high-Z
(active to High-Z)
Clock (C/C) rise to Low-Z
Clock phase jitter
DLL lock time (K, C)
K static to DLL reset
[20, 21]
CHZ
is less than t
(continued)
Description
CLZ
[24, 25]
and t
[23]
CHZ
[24, 25]
less than t
[23]
AC Test Loads and
KHKH
CO
–0.45
–0.27
–0.45
1024
1.24
1.24
Min Max Min Max Min Max Min Max Min Max
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
.
300 MHz
30
0.45
0.45
0.27
0.45
0.20
Waveforms. Transition is measured ±100 mV from steady-state voltage.
–0.45
–0.45
–0.27
–0.45
1024
1.35
1.35
278 MHz
30
0.45
0.45
0.27
0.45
0.20
–0.45
–0.45
–0.30
–0.45
1024
1.55
1.55
250 MHz
30
0.45
0.45
0.30
0.45
0.20
–0.45
–0.45
–0.35
–0.45
1024
1.95
1.95
200 MHz
30
CY7C1518AV18
CY7C1520AV18
0.45
0.45
0.35
0.45
0.20
–0.50
–0.50
–0.40
–0.50
1024
2.45
2.45
167 MHz
30
KC Var
Page 23 of 28
0.50
0.50
0.40
0.50
0.20
) is already
Cycles
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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