CY7C1480BV33-200BZXI Cypress Semiconductor Corp, CY7C1480BV33-200BZXI Datasheet - Page 10

• Manufacturer Part Number: CY7C1480BV33-200BZXI
• Description: IC SRAM 72MBIT 200MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480BV33-200BZXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The truth table for CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 follows.
Truth Table
Document #: 001-15145 Rev. *A
Notes
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle,Suspend Burst
Write Cycle,Suspend Burst
2. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tri-state. OE is a do not care for
the remainder of the write cycle.
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Operation
Add. Used
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
CE
H
X
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
1
CE
X
H
H
H
H
H
X
X
X
X
X
L
X
L
X
X
X
X
X
X
X
X
X
2
CE
H
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
3
ZZ ADSP
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
X
L
L
X
L
L
X
X
X
X
X
X
CY7C1482BV33, CY7C1486BV33
ADSC
[2, 3, 4, 5, 6
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
X
. Writes may occur only on subsequent clocks after the
ADV WRITE OE CLK
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
CY7C1480BV33
X
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H
L-H
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H
X
Page 10 of 34
Tri-State
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D
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