CY7C1480BV33-200AXC Cypress Semiconductor Corp, CY7C1480BV33-200AXC Datasheet
CY7C1480BV33-200AXC
Specifications of CY7C1480BV33-200AXC
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CY7C1480BV33-200AXC Summary of contents
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... GW when active LOW causes all bytes to be written. The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. For best practices recommendations, refer to the Cypress application note “ ...
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... Logic Block Diagram – CY7C1480BV33 (2 M × 36 A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP BYTE BW D WRITE REGISTER BYTE BW C WRITE REGISTER BYTE BW B WRITE REGISTER DQ DQP BYTE BW A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL Logic Block Diagram – CY7C1482BV33 (4 M × 18) ...
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... WRITE DRIVER WRITE DRIVER MEMORY ARRAY DQ , DQP D D WRITE DRIVER DQ , DQP C C WRITE DRIVER DQ , DQP B B WRITE DRIVER DQ , DQP A A WRITE DRIVER PIPELINED ENABLE CY7C1480BV33 OUTPUT OUTPUT DQs SENSE BUFFERS REGISTERS AMPS DQP A E DQP B DQP C DQP D DQP E DQP F DQP G DQP H INPUT ...
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... TAP Controller State Diagram ....................................... 15 TAP Controller Block Diagram ...................................... 16 3.3 V TAP AC Test Conditions ....................................... 17 3.3 V TAP AC Output Load Equivalent ......................... 17 2.5 V TAP AC Test Conditions ....................................... 17 Document Number: 001-15145 Rev. *E CY7C1480BV33 CY7C1482BV33, CY7C1486BV33 2.5 V TAP AC Output Load Equivalent ......................... 17 TAP DC Electrical Characteristics and Operating Conditions ..................................................... 17 TAP AC Switching Characteristics ............................... 18 TAP Timing ...
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... Pin Configurations Figure 1. CY7C1480BV33 100-pin TQFP Pinout DQP DQc DDQ V 5 SSQ SSQ V 11 DDQ CY7C1480BV33 × 36 DDQ V 21 SSQ SSQ V 27 DDQ DQP D 30 Document Number: 001-15145 Rev. *E CY7C1482BV33, CY7C1486BV33 Figure 2. CY7C1482BV33 100-pin TQFP Pinout DQP DDQ 4 DDQ SSQ 5 SSQ ...
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... DDQ DDQ N DQP DDQ MODE NC/288M NC/144M A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ MODE A A Document Number: 001-15145 Rev. *E CY7C1482BV33, CY7C1486BV33 CY7C1480BV33 (2 M × 36 BWE CLK TDI A1 TDO A A0 TCK A TMS CY7C1482BV33 (4 M × 18) ...
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... ADSC ADSP ADV 2 A NC/288M BWE BWS C G NC/144M NC/576M BWS NC/ DDQ DDQ DDQ DDQ DDQ DDQ MODE TDI CY7C1480BV33 BWS BWS BWS DQ DQ BWS DQP DQP DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DQP DQP DDQ DDQ ...
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... The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP condition. Power Supply Inputs to the Core of the Device. Ground for the Core of the Device. Ground for the IO Circuitry. serves as ground for the core and the IO circuitry. SS CY7C1480BV33 , CE , and CE are sampled ...
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... Maximum access delay from the clock rise ( 3.0 ns (250 MHz device). CO The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 support secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that use a linear burst sequence ...
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... DQs inputs. Doing so tri-states the output drivers safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 provide a 2-bit wraparound counter, fed by A1: A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications ...
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... Truth Table The truth table for CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 follows. Operation Add. Used Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Deselect Cycle, Power Down None Sleep Mode, Power Down ...
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... Truth Table for Read/Write The read/write truth table for CY7C1480BV33 follows. Function (CY7C1480BV33) Read Read Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Bytes B, A Write Byte C – (DQ and DQP ) C C Write Bytes C, A Write Bytes C, B Write Bytes Write Byte D – ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1480BV33 ). CH Page [+] Feedback ...
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... TAP Controller State Diagram TEST-LOGIC 1 RESET 0 RUN-TEST/ 0 IDLE Document Number: 001-15145 Rev. *E CY7C1482BV33, CY7C1486BV33 1 1 SELECT DR-SCA CAPTURE-DR 0 SHIFT- EXIT1-DR 0 PAUSE- EXIT2-DR 1 UPDATE- CY7C1480BV33 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1-IR 0 PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...
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... TAP Controller Block Diagram TDI TCK TM S Document Number: 001-15145 Rev. *E CY7C1482BV33, CY7C1486BV33 0 Bypass Register Selection Instruction Register Circuitry Identification Register Boundary Scan Register TAP CONTROLLER CY7C1480BV33 Selection TDO Circuitry Page [+] Feedback ...
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... DDQ I = 100 µ 3 DDQ V = 2.5 V DDQ V = 3.3 V DDQ V = 2.5 V DDQ V = 3.3 V DDQ V = 2.5 V DDQ GND < V < DDQ CY7C1480BV33 to 2 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 – V 2.0 – V 2.9 – V 2.1 – V – 0.4 V – 0.4 V – 0.2 V – ...
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... Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-15145 Rev. *E CY7C1482BV33, CY7C1486BV33 Description Figure 3. TAP Timing TDIS t TDIH t TDOX DON’ UNDEFINED / ns CY7C1480BV33 Min Max Unit 50 – – 20 MHz 20 – 20 – – – 5 – 5 – 5 – 5 – ...
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... Do Not Use: This instruction is reserved for future use. 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1480BV33 Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density ...
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... C11 P10 53 G10 R9 54 F10 R10 55 E10 R11 56 A10 N11 57 B10 M11 58 A9 L11 59 B9 M10 60 A8 Bit # 165-ball P10 R10 27 R11 28 M10 29 L10 30 K10 31 J10 32 H11 33 G11 34 F11 35 E11 36 D11 CY7C1480BV33 Bit # 165-ball Bit # 165-ball ID 37 C11 38 A11 39 A10 40 B10 ...
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... L11 W6 71 L10 J11 V5 74 J10 U5 75 H11 U6 76 H10 W7 77 G11 V7 78 G10 U7 79 F11 V8 80 F10 V9 81 E10 W11 82 E11 W10 83 D11 V11 84 D10 CY7C1480BV33 Bit # 209-ball ID 85 C11 86 C10 87 B11 88 B10 89 A11 90 A10 100 A8 101 B4 102 B3 103 C3 104 C4 ...
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... MAX CYC 6.0 ns cycle, 167 MHz /2). Undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1480BV33 Ambient DDQ Temperature 0 C to +70 C 3.3 V– 2.5 V – 10 –40 C to +85 C Min Max 3 ...
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... 2.5 V DDQ 100-pin TQFP Test Conditions Package Test conditions follow 24.63 standard test methods and procedures for measuring 2.28 thermal impedance, according to EIA/JESD51. CY7C1480BV33 Min Max Unit – 120 mA – 245 mA – 245 mA – 245 mA – 135 mA 165-ball FBGA 209-ball FBGA ...
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... Figure 4. AC Test Loads and Waveforms R = 317 3 DDQ GND 351 INCLUDING JIG AND (b) SCOPE R = 1667 2 DDQ GND 1538 INCLUDING JIG AND (b) SCOPE CY7C1480BV33 ALL INPUT PULSES 90% 90% 10% 10% (c) ALL INPUT PULSES 90% 90% 10% 10% (c) Page [+] Feedback ...
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... V Figure 4 on page is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same data OELZ CHZ CLZ CY7C1480BV33 200 MHz 167 MHz Min Max Min Max – 1 – ...
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... OEV OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH, and CE is LOW. When CE is HIGH CY7C1480BV33 A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... A2 t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED is HIGH, and CE is LOW. When CE is HIGH LOW. X CY7C1480BV33 ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVS ADVH D( D(A3 Extended BURST WRITE is HIGH LOW HIGH ...
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... Document Number: 001-15145 Rev. *E CY7C1482BV33, CY7C1486BV33 Figure 5. Read/Write Cycle Timing WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED is HIGH, and CE is LOW. When CE is HIGH CY7C1480BV33 A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs is HIGH LOW HIGH Page [+] Feedback ...
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... Device must be deselected when entering ZZ mode. See the section 25. DQs are in High Z when exiting ZZ sleep mode. Document Number: 001-15145 Rev. *E CY7C1482BV33, CY7C1486BV33 Figure 6. ZZ Mode Timing t RZZI DESELECT or READ Only High-Z DON’T CARE Truth Table on page 11 for all possible signal conditions to deselect the device. CY7C1480BV33 t ZZREC Page [+] Feedback ...
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... CY7C1480BV33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 × 17 × 1.4 mm) Pb-free CY7C1480BV33-167AXI 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 200 CY7C1480BV33-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free CY7C1482BV33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 × 17 × 1.4 mm) ...
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... Package Diagrams Document Number: 001-15145 Rev. *E CY7C1482BV33, CY7C1486BV33 Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) CY7C1480BV33 51-85050 *D Page [+] Feedback ...
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... Package Diagrams (continued) Figure 8. 165-ball FBGA (15 × 17 × 1.4 mm) Document Number: 001-15145 Rev. *E CY7C1480BV33 CY7C1482BV33, CY7C1486BV33 51-85165 *B Page [+] Feedback ...
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... Package Diagrams (continued) Figure 9. 209-ball FBGA (14 × 22 × 1.76 mm) Document Number: 001-15145 Rev. *E CY7C1480BV33 CY7C1482BV33, CY7C1486BV33 51-85167 *A Page [+] Feedback ...
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... Document History Page Document Title: CY7C1480BV33/CY7C1482BV33/CY7C1486BV33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM Document Number: 001-15145 Submission REV. ECN NO. Date ** 1024385 See ECN VKN/KKVTMP New Datasheet *A 2183566 See ECN *B 2898663 03/24/2010 *C 2905654 06/04/2010 *D 3069168 10/23/10 *E 3207715 03/28/2011 Document Number: 001-15145 Rev. *E CY7C1482BV33, CY7C1486BV33 Orig ...
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... Document Number: 001-15145 Rev. *E i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C1482BV33, CY7C1486BV33 cypress.com/go/plc Revised March 28, 2011 CY7C1480BV33 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...