CY7C1480BV33-200AXC Cypress Semiconductor Corp, CY7C1480BV33-200AXC Datasheet - Page 14

• Manufacturer Part Number: CY7C1480BV33-200AXC
• Description: CY7C1480BV33-200AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480BV33-200AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Number: 001-15145 Rev. *E
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in
Codes on page
RESERVED and must not be used. The other five instructions
are described in detail in this section.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO
buffers. The SRAM does not implement the 1149.1 commands
EXTEST
SAMPLE/PRELOAD; rather, it performs a capture of the IO
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction after it is shifted in, the TAP
controller must be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction, which must be
executed whenever the instruction register is loaded with all
zeros. EXTEST is not implemented in this SRAM TAP
controller, and therefore this device is not compliant to 1149.1.
The TAP controller does recognize an all-zero instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the
instruction, EXTEST places the SRAM outputs in a High Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and
enables the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
at power up or whenever the TAP controller is in a test logic
reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High Z state.
two
or
instructions.
INTEST
19. Three of these instructions are listed as
Unlike
or
the
the
PRELOAD
SAMPLE/PRELOAD
Identification
portion
of
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
Be aware that the TAP controller clock can only operate at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal when in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (t
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
After the data is captured, the data is shifted out by putting the
TAP into the Shift-DR state. This places the boundary scan
register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state when
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
CY7C1482BV33, CY7C1486BV33
CS
plus t
CH
).
CY7C1480BV33
Page 14 of 35
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