CY7C1515JV18-167BZI Cypress Semiconductor Corp, CY7C1515JV18-167BZI Datasheet
CY7C1515JV18-167BZI
Specifications of CY7C1515JV18-167BZI
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CY7C1515JV18-167BZI Summary of contents
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... DDR interfaces. Each address location is associated with four 18-bit words (CY7C1513JV18), or 36-bit words (CY7C1515JV18) that burst sequentially into or out of the device. Because data is trans- ferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus ‘ ...
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... Logic Block Diagram (CY7C1513JV18 [17:0] 20 Address A (19:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram (CY7C1515JV18 [35:0] 19 Address A (18:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document Number: 001-12560 Rev. *F Write Write Write ...
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... Pin Configuration The pin configuration for CY7C1513JV18 and CY7C1515JV18 follow NC/144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO TCK NC/288M A B Q27 ...
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... Internally, the device is organized arrays each 18) for CY7C1513JV18 and arrays each of 512K x 36) for CY7C1515JV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1513JV18 and 19 address inputs for CY7C1515JV18. These inputs are ignored when the appro- priate port is deselected ...
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... Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC REF Reference measurement points. V Power Supply Power Supply Inputs to the Core of the Device Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-12560 Rev. *F CY7C1513JV18 CY7C1515JV18 Pin Description Page [+] Feedback ...
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... Each access consists of four 18-bit data transfers in the case of CY7C1513JV18, and four 36-bit data transfers in the case of CY7C1515JV18 in two clock cycles. This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or ...
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... All pending transactions (read and write) are completed before the device is deselected. Document Number: 001-12560 Rev. *F CY7C1513JV18 CY7C1515JV18 Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V to allow the SRAM to adjust its output SS driver impedance ...
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... MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed 50ohms Truth Table The truth table for CY7C1513JV18, and CY7C1515JV18 follows. Operation K RPS WPS [8] Write Cycle: L-H H Load address on the rising edge of K; input write data on two consecutive K and K rising edges. [9] Read Cycle: ...
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... L–H – No data is written into the devices during this portion of a write operation – L–H No data is written into the devices during this portion of a write operation. Write Cycle Descriptions The write cycle description table for CY7C1515JV18 follows. BWS BWS BWS BWS ...
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... TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. CY7C1513JV18 CY7C1515JV18 TAP Controller Block Diagram on ) when the SS on page 16 shows the order in which ...
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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-12560 Rev. *F CY7C1513JV18 CY7C1515JV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...
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... Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-12560 Rev. *F [11] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1513JV18 CY7C1515JV18 1 SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...
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... Boundary Scan Register TAP Controller Test Conditions = −2 −100 μ 2 100 μ GND ≤ V ≤ − /2), Undershoot: V (AC) > 1.5V (Pulse width less than t CYC IL CY7C1513JV18 CY7C1515JV18 Selection TDO Circuitry Min Max Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 0.35V V DD μA – ...
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... Test conditions are specified using the load in TAP AC test conditions. t Document Number: 001-12560 Rev. *F Description [16] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50Ω TMSH t TMSS t TDIS t TDIH t TDOV / ns CY7C1513JV18 CY7C1515JV18 Min Max Unit 50 20 MHz ALL INPUT PULSES 0.9V t TCYC t TDOX Page ...
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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-12560 Rev. *F Value CY7C1515JV18 000 000 11010011011100100 00000110100 00000110100 1 Description CY7C1513JV18 CY7C1515JV18 Description Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. 1 Indicates the presence register. Bit Size ...
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... Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D 11B 70 3C 11C 10B 73 3E 11A 74 2D 10A CY7C1513JV18 CY7C1515JV18 Bit # Bump 100 2P 101 1P 102 3R 103 4R 104 4P 105 5P 106 5N 107 5R 108 Internal Page [+] Feedback ...
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... DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide1024 cycles stable clock to relock to the desired clock frequency. . REF Figure 3. Power Up Waveforms > 1024 Stable clock Stable DDQ Stable (< +/- 0.1V DC per 50ns ) / DDQ Fix High (or tie to V DDQ ) CY7C1513JV18 CY7C1515JV18 . KC Var Start Normal Operation Page [+] Feedback ...
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... MHz (x18) (x36) (min) within 200 ms. During this time V < V and /2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1513JV18 CY7C1515JV18 Test Con- Description Typ Max* ditions Logical 25°C 320 368 Single-Bit Upsets Logical 25° ...
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... R = 50Ω REF OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250Ω INCLUDING JIG AND (b) SCOPE /I and load capacitance shown in ( CY7C1513JV18 CY7C1515JV18 Min Typ Max 405 405 380 380 340 340 Min Typ Max V + 0.2 – – REF – – V – 0.2 ...
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... An input jitter of 200 ps (t KHKH AC Test Loads and Waveforms on page 19. Transition is measured ± 100 mV from steady-state voltage. and t less than t . CLZ CHZ CO CY7C1513JV18 CY7C1515JV18 300 MHz 250 MHz 167 MHz Min Max Min Max Min Max 3.3 8.4 4.0 8 ...
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... WRITE READ WRITE KHKH D13 D10 D11 D12 Q00 Q01 Q02 CLZ t DOH t KHKH t CCQO t CQOH t CCQO t CQOH DON’T CARE CY7C1513JV18 CY7C1515JV18 NOP D30 D31 D32 D33 Q22 Q03 Q20 Q21 Q23 t CHZ t CQDOH t CQD UNDEFINED Page [+] Feedback ...
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... CY7C1513JV18-300BZC CY7C1515JV18-300BZC CY7C1513JV18-300BZXC CY7C1515JV18-300BZXC CY7C1515JV18-300BZI 250 CY7C1513JV18-250BZXC 167 CY7C1515JV18-167BZI Document Number: 001-12560 Rev. *F www.cypress.com Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...
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... SEATING PLANE C Document Number: 001-12560 Rev CY7C1513JV18 CY7C1515JV18 BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. +0.14 Ø0.50 (165X) -0. 1.00 5.00 10.00 B 15.00±0.10 NOTES : 0.15(4X) SOLDER PAD TYPE : NON SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.65g JEDEC REFERENCE : MO-216 / ISSUE E PACKAGE CODE : BB0AD ...
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... Document History Page Document Title: CY7C1513JV18/CY7C1515JV18, 72-Mbit QDR Document Number: 001-12560 ECN No. Submission Orig. of Rev. Date Change ** 808457 See ECN VKN *A 1273951 See ECN VKN *B 1462588 See ECN VKN/AESA Converted from preliminary to final *C 2189567 See ECN VKN/AESA Minor Change-Moved to the external web ...