DS2502-E48+ Maxim Integrated Products, DS2502-E48+ Datasheet
DS2502-E48+
Specifications of DS2502-E48+
Related parts for DS2502-E48+
DS2502-E48+ Summary of contents
Page 1
... Directly connects to a single port pin of a microprocessor and communicates 16.3 kbits per second 8-bit family code specifies DS2502 communications requirements to reader Presence detector acknowledges when the reader first applies voltage Low cost TO-92 or 8-pin SO, SOT-23 (3- ...
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... The DS2502 1Kb Add-Only Memory identifies and stores relevant information about the product to which it is associated. This lot- or product-specific information can be accessed with minimal interface- for example, a single port pin of a microcontroller. The DS2502 consists of a factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (09h) plus 1Kb of EPROM which is user-programmable. The power to program and read the DS2502 is derived ...
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... LASERED ROM Each DS2502 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3). The 64-bit ROM and ROM Function Control section allow the DS2502 to operate as a 1-Wire device and follow the 1-Wire protocol detailed in the section “ ...
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HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 64-BIT LASERED ROM Figure 3 8–Bit CRC Code MSB 1-WIRE CRC GENERATOR Figure 4 48–Bit Serial Number LSB MSB 8–Bit Family Code (09h) LSB MSB LSB ...
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... EPROM The memory map in Figure 5 shows the 1024-bit EPROM section of the DS2502 which is configured as four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit CRC from the DS2502 that confirms proper receipt of the data ...
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... To execute a read sequence, the starting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. All bits transferred to the DS2502 and received back by the bus master are sent least significant bit first. ...
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... MEMORY FUNCTION FLOW CHART Figure ...
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... MEMORY FUNCTION FLOW CHART Figure 6 (cont’d) LEGEND: DECISION MADE BY THE MASTER DECISION MADE BYDS2502 ...
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... MEMORY FUNCTION FLOW CHART Figure 6 (cont’ ...
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... Read Status command supplies a 8-bit CRC that is based on and always is consistent with the current data stored in the EPROM Status data field. After the 8-bit CRC is read, the bus master will receive logical 1s from the DS2502 until a reset pulse is issued. The Read Status command sequence can be ended at any point by issuing a reset pulse. ...
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... EPROM data field. After the 8-bit CRC of the last page is read, the bus master will receive logical 1s from the DS2502 until a reset pulse is issued. The Read Data/Generate 8-Bit CRC command sequence can be exited at any point by issuing a reset pulse ...
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... The bus master will issue the next byte of data using eight write time slots. As the DS2502 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address; the result is an 8-bit CRC of the new data byte and the LSB of the new address ...
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... DS2502 will not be able to determine if the 8-bit CRC calculated by the bus master agrees with the 8-bit CRC calculated by the DS2502 incorrect CRC is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS2502. Also note that the DS2502 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte ...
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... This command allows the bus master to read the DS2502’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can be used only if there is a single DS2502 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result) ...
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... DS2502 EQUIVALENT CIRCUIT Figure 7 BUS MASTER CIRCUIT Figure ...
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ROM FUNCTIONS FLOW CHART Figure ...
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... DS2502. During write time slots, the delay circuit determines when the DS2502 will sample the data line. For a read data time slot “0” transmitted, the delay circuit determines how long the DS2502 will hold the data line low overriding the “1” generated by the master. ...
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... CRC GENERATION The DS2502 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2502 to determine if the ROM data has been received error-free by the bus master. The equivalent ...
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... DS2502 DS2502 SAMPLING WINDOW 60 s t < 120 s SLOT 1 s t < 15 s LOW1 1 s t < REC DS2502 SAMPLING WINDOW 60 s t < 120 s < t LOW0 SLOT 1 s t < REC 60 s t < 120 s SLOT 1 ...
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PROGRAM PULSE TIMING DIAGRAM Figure ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the ...
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NOTES: 1. All voltages are referenced to ground external pullup voltage. PUP 3. Input load is to ground additional reset or communication sequence cannot begin until the reset high time has expired. 5. Read data ...
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REVISION HISTORY REVISION DATE Added note to Figure 10 that changed t Added VEPR specification. 12/09 Changed t to 960s maximum. RSTL Added notes 13 and 14. DESCRIPTION to 960s maximum. RSTL PAGES CHANGED ...