SST49LF016C-33-4C-NHE Microchip Technology, SST49LF016C-33-4C-NHE Datasheet - Page 11
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SST49LF016C-33-4C-NHE
Manufacturer Part Number
SST49LF016C-33-4C-NHE
Description
IC FLASH SER LPC 16MBIT 32PLCC
Manufacturer
Microchip Technology
Datasheets
1.SST49LF080A-33-4C-NHE.pdf
(2 pages)
2.SST49LF080A-33-4C-NHE.pdf
(2 pages)
3.SST49LF016C-33-4C-NHE.pdf
(36 pages)
Specifications of SST49LF016C-33-4C-NHE
Memory Type
FLASH
Memory Size
16M (2M x 8)
Operating Temperature
0°C ~ 85°C
Package / Case
32-PLCC
Format - Memory
FLASH
Speed
33MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Data Bus Width
8 bit
Architecture
Sectored
Interface Type
Parallel, Serial
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
18 mA
Mounting Style
SMD/SMT
Organization
4 KB x 512
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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ST
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Part Number:
SST49LF016C-33-4C-NHE
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Quantity:
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Quantity:
20 000
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SST49LF016C-33-4C-NHE-T
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Microchip Technology
Quantity:
10 000
16 Mbit LPC Serial Flash
SST49LF016C
Firmware Memory Write Cycle
TABLE 5: Firmware Memory Write Cycle
©2008 Silicon Storage Technology, Inc.
FIGURE 7: Firmware Memory Write Cycle Waveform
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
(A+1)
(A+2)
(A+3)
(A+4)
(A+5)
11-A
LFRAME#
3-9
10
1
2
LAD[3:0]
LCLK
MADDR
RSYNC
START
MSIZE
IDSEL
Name
Field
DATA
TAR0
TAR1
TAR0
TAR1
1110b 0000b
Start
IDSEL
A[27:24]
Field Contents
0000 to 1111
1111 (float)
1111 (float)
A[23:20] A[19:16]
LAD[3:0]
YYYY
KKKK
ZZZZ
1110
1111
0000
1111
1
MADDR
A[15:12]
A[11:8]
OUT then Float
Float then OUT The SST49LF016C takes control of the bus during this
IN then Float
Float then IN
Direction
LAD[3:0]
A[7:4]
OUT
IN
IN
IN
IN
IN
11
A[3:0]
MSIZE
KKKKb
Comments
LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) will be recognized. The START field contents
(1110b) indicate a Firmware Memory Write cycle.
Indicates which SST49LF016C device should respond.
If the IDSEL (ID select) field matches the value of
ID[3:0], then that particular device will respond to the
whole bus cycle.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
transferred during multi-byte operations.
Device supports 1, 2, and 4 Bytes write with MSIZE =
0, 1, or 2, and KKKK=0000b, 0001b, or 0010b.
A=(10+2
Least significant nibble entered first.
‘1’s and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
A=(10+2
cycle.
A=(10+2
“ready sync” (RSYNC) and outputs the values 0000,
indicating that it has received data or a flash command.
A=(10+2
all ‘1’s and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround
cycle”. A=(10+2
The host resumes control of the bus during this cycle.
A=(10+2
The MSIZE field indicates how many bytes will be
In this clock cycle, the master has driven the bus to all
During this clock cycle, the SST49LF016C generates a
In this clock cycle, the SST49LF016C drives the bus to
D
0
[3:0]
D
0
[7:4]
n+1
n+1
n+1
n+1
n+1
DATA
); n = MSIZE
); n = MSIZE
); n = MSIZE
); n = MSIZE
); n = MSIZE
n+1
Dn[3:0]
); n = MSIZE
Dn[7:4]
TAR0
1111b
Tri-State
TAR1
RSYNC
S71237-08-000
0000b
1237 F04.0
TAR
Data Sheet
T5.0 1237
5/08