CY7C1168V18-375BZC Cypress Semiconductor Corp, CY7C1168V18-375BZC Datasheet

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... K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words (CY7C1166V18), or 9-bit words (CY7C1177V18), or 18-bit words (CY7C1168V18), or 36-bit words (CY7C1170V18) that burst sequentially into or out of the device. Asynchronous inputs include output impedance matching input (ZQ) ...

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... Logic Block Diagram (CY7C1177V18 (19:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [0] Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Write Write Reg Reg Output Logic Control Read Data Reg Reg. Reg. 8 Reg. Write Write Reg Reg Output Logic Control Read Data Reg ...

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... Logic Block Diagram (CY7C1168V18 (18:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1170V18 (17:0) Address Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 ...

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... NC NC DQ5 DOFF REF DDQ DQ6 DQ7 R TDO TCK NC/72M DQ4 DQ5 DOFF REF DDQ DQ6 DQ7 R TDO TCK A Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 CY7C1166V18 ( NC/144M R/W NWS NC/288M K NWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ QVLD ...

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... NC NC DQ20 F NC DQ30 DQ21 G NC DQ31 DQ22 DOFF REF DDQ DQ32 DQ23 L NC DQ33 DQ24 DQ34 N NC DQ35 DQ25 DQ26 R TDO TCK A Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 CY7C1168V18 ( NC/144M K R/W BWS 1 A NC/288M K BWS DDQ DDQ ...

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... These address inputs are multiplexed for both read and write operations. Internally, the device is organized (two arrays each of1M x 8) for CY7C1166V18 (two arrays each for CY7C1177V18 (two arrays each of 512K x 18) for CY7C1168V18, and 512K x 36 (two arrays each of 256K x 18) for CY7C1170V18. All the address inputs are ignored when the appropriate port is deselected ...

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... Power Supply Power Supply Inputs to the Core of the Device Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Pin Description output impedance are set to 0.2 x RQ, where resistor [x:0] , which DDQ Page [+] Feedback ...

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... CY7C1166V18, CY7C1177V18, and CY7C1170V18. Read Operations The CY7C1168V18 is organized internally as a single array 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K) ...

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... Source CLK Source CLK Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2 Truth Table The truth table for the CY7C1166V18, CY7C1177V18, CY7C1168V18, and CY7C1170V18 follows. Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: (2.5 Cycle Latency) Load address ...

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... Write Cycle Descriptions The write cycle descriptions of CY7C1166V18 and CY7C1168V18 follows. BWS / BWS / NWS NWS L–H – During the Data portion of a write sequence: CY7C1166V18 − both nibbles (D CY7C1168V18 − both bytes ( – L-H During the Data portion of a write sequence: CY7C1166V18 − ...

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... – Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 [ Comments – During the data portion of a write sequence, all four bytes (D the device. L-H During the data portion of a write sequence, all four bytes (D the device. – During the data portion of a write sequence, only the lower byte (D into the device ...

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... TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Instruction Register Load three-bit instructions serially into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in page 15 ...

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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 PRELOAD enables an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells be- fore the selection of another boundary scan test operation. ...

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... TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 [9] Figure 2. Tap Controller State Diagram 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- ...

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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 11. Overshoot: V (AC) < 0.35V (pulse width less than t IH DDQ 12. All voltage refer to ground. Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Figure 3. Tap Controller Block Diagram 0 Bypass Register Instruction Register 29 ...

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... Output Times t TCK Clock LOW to TDO Valid TDOV t TCK Clock LOW to TDO Invalid TDOX TAP Timing and Test Condition The Tap Timing and Test Conditions for the CY7C1166V18, CY7C1177V18, CY7C1168V18, and CY7C1170V18 follows. 0.9V TDO Z = 50Ω 0 (a) GND Test Clock ...

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... SAMPLE Z 010 RESERVED 011 SAMPLE/PRELOAD 100 RESERVED 101 RESERVED 110 BYPASS 111 Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Value CY7C1177V18 CY7C1168V18 000 000 11010111000001101 11010111000010101 00000110100 00000110100 1 1 Description Captures the input output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO ...

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... Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Bump ID Bit # Bump ID 11H 54 7B 10G 11F 57 5B 11G 10F 60 5C 11E 61 4B 10E 62 3A 10D 10C 65 2B 11D 66 3B ...

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... SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency. REF Figure 5. Power Up Waveforms > 2048 Stable Clock DDQ Stable (< + 0.1V DC per 50 ns) Fix HIGH (tie to V DDQ ) CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 . KC Var Start Normal Operation Page [+] Feedback ...

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... Test Conditions (min) within 200 ms. During this time V < V and /2)/(RQ/5) for values of 175Ω < RQ < 350Ω. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Ambient [15] Temperature DDQ 0°C to +70°C 1.8 ± 0.1V 1. –40°C to +85°C ...

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... Note 20. Unless otherwise noted, test conditions are based on a signal transition time of 2V/ns, timing reference levels of 0.75V, V pulse levels of 0.25V to 1.25V, and output loading of the specified I Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Test Conditions T = 25° MHz 1.8V ...

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... An input jitter of 200 ps (t KHKH on page 21. Transition is measured ± 100 mV from steady-state “AC Test Loads and Waveforms” and t less than t . CLZ CHZ CO CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 375 MHz 333 MHz 300 MHz 1 – 1 – 1 – 3.0 8 ...

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... Latency = 2.5 Cycles Notes 28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e 29. Outputs are disabled (High-Z) one clock cycle after a NOP. Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 NOP NOP NOP WRITE ...

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... CY7C1177V18-400BZC CY7C1168V18-400BZC CY7C1170V18-400BZC CY7C1166V18-400BZXC CY7C1177V18-400BZXC CY7C1168V18-400BZXC CY7C1170V18-400BZXC CY7C1166V18-400BZI CY7C1177V18-400BZI CY7C1168V18-400BZI CY7C1170V18-400BZI CY7C1166V18-400BZXI CY7C1177V18-400BZXI CY7C1168V18-400BZXI CY7C1170V18-400BZXI 375 CY7C1166V18-375BZC CY7C1177V18-375BZC CY7C1168V18-375BZC CY7C1170V18-375BZC CY7C1166V18-375BZXC CY7C1177V18-375BZXC CY7C1168V18-375BZXC CY7C1170V18-375BZXC CY7C1166V18-375BZI CY7C1177V18-375BZI CY7C1168V18-375BZI CY7C1170V18-375BZI CY7C1166V18-375BZXI CY7C1177V18-375BZXI CY7C1168V18-375BZXI CY7C1170V18-375BZXI Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Package ...

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... CY7C1166V18-300BZXI CY7C1177V18-300BZXI CY7C1168V18-300BZXI CY7C1170V18-300BZXI Document Number: 001-06620 Rev. *D CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85180 165-Ball Fine Pitch Ball Grid Array ( ...

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... Package Diagram Figure 8. 165-Ball FBGA ( 1.4 mm), 51-85180 TOP VIEW PIN 1 CORNER 13.00±0.10 SEATING PLANE C Document Number: 001-06620 Rev 0.15(4X) CY7C1166V18, CY7C1177V18 CY7C1168V18, CY7C1170V18 BOTTOM VIEW PIN 1 CORNER Ø0. Ø0. 0.06 Ø0.50 (165X) +0. 1.00 5.00 10.00 13.00±0.10 NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0 ...

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... Document History Page Document Title: CY7C1166V18/CY7C1177V18/CY7C1168V18/CY7C1170V18, 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Document Number: 001-06620 Orig. of REV. ECN No. Issue Date Change ** 430351 See ECN *A 461654 See ECN *B 497629 See ECN *C 1175245 See ECN VKN/KKVTMP Converted from preliminary to final ...