C8051F531-ITR Silicon Labs, C8051F531-ITR Datasheet - Page 164
C8051F531-ITR
Manufacturer Part Number
C8051F531-ITR
Description
8-bit Microcontrollers - MCU 8KB 12ADC 125C 20Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F536-ITR.pdf
(220 pages)
Specifications of C8051F531-ITR
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
8 KB
Data Ram Size
256 B
On-chip Adc
Yes
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
16
Interface Type
SPI, UART
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
16
Number Of Timers
3
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
2500
Supply Voltage - Max
2.7 V, 5.25 V
Supply Voltage - Min
2 V, 2.7 V
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C8051F52x/F53x
17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A)
Important Note: This chapter assumes an understanding of the Local Interconnect Network (LIN) proto-
col. For more information about the LIN protocol, including specifications, please refer to the LIN consor-
tium (http://www.lin-subbus.org/).
LIN is an asynchronous, serial communications interface used primarily in automotive networks. The Sili-
con Laboratories LIN controller is compliant to the 2.1 Specification, implements a complete hardware LIN
interface, and includes the following features:
Note: The minimum system clock (SYSCLK) required when using the LIN peripheral is 8 MHz.
The LIN peripheral has four main components:
164
Selectable Master and Slave modes.
Automatic baud rate option in slave mode
The internal oscillator is accurate to within 0.5% of 24.5 MHz across the entire temperature range and
for VDD voltages greater than or equal to the minimum output of the on-chip voltage regulator, so an
external oscillator is not necessary for master mode operation for most systems.
1. LIN Access Registers—Provide the interface between the MCU core and the LIN peripheral.
2. LIN Data Registers—Where transmitted and received message data bytes are stored.
3. LIN Control Registers—Control the functionality of the LIN interface.
4. Control State Machine and Bit Streaming Logic—Contains the hardware that serializes mes-
sages and controls the bus timing of the controller.
RX
TX
Indirectly Addressed Registers
Registers
LIN Data
Control State Machine
LIN Controller
Figure 17.1. LIN Block Diagram
C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A
LIN Control
Registers
Rev. 1.4
8051 MCU Core
LINADDR
LINDATA
LINCF
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