CYD18S18V18-200BBAXC Cypress Semiconductor Corp, CYD18S18V18-200BBAXC Datasheet - Page 37

• Manufacturer Part Number: CYD18S18V18-200BBAXC
• Description: IC SRAM 18MBIT 200MHZ 256LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYD18S18V18-200BBAXC

• Memory Size: 18M (1M x 18)
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.42 V ~ 1.58 V, 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-LFBGA
• Memory Configuration: 1M X 18
• Clock Frequency: 77MHz
• Access Time: 3.3ns
• Supply Voltage Range: 1.42V To 1.58V, 1.7V To 1.9V
• Memory Case Style: BGA
• No. Of Pins: 256
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2036

Switching Waveforms
Notes
Document Number: 38-06082 Rev. *J
59. When OE = V
60. Two dummy writes are issued to accomplish bus turnaround. The third instruction is the first valid write.
61. Chip enable or all byte enables are held inactive during the two dummy writes to avoid data corruption.
62. OE is deasserted and t
63. Any write scheduled to complete after OE is deasserted is pre-empted.
R/W
DQ
R/W
OE
C
DQ
A
C
A
DQ
DQ
t
CKLZ2
A
IL
A
x-2
, the last read operation is enabled to complete before the DQ bus is tri-stated and the user is enabled to drive write data.
x
x-2
x
t
CD2
t
CH
t
CYC
t
OHZ
CYC
enabled to elapse before the first write operation is issued.
DQ
t
DQ
t
CL
t
SAC
SAC
Figure 27. READ-to-WRITE for Pipelined Mode (OE Controlled)
A
x-1
Figure 26. READ-to-WRITE for Pipelined Mode (OE = V
x-1
x+1
(continued)
t
t
t
HAC
HAC
DC
DQ
A
x
DQ
n
A
x
t
x+2
OHZ
t
CKHZ2
t
SD
DQ
DQ
A
n
n
n
t
HD
DQ
DQ
A
A
n+1
n+1
n+1
n+1
IL
)
[59, 60, 61]
t
SAC
DQ
t
[62, 63]
SD
DQ
A
A
n+2
n+2
n+2
n+2
t
t
HAC
HD
DQ
A
n+3
n+3
Page 37 of 52
FullFlex
[+] Feedback