ZLF645S2864GP0001 Maxim Integrated, ZLF645S2864GP0001 Datasheet - Page 73

• Manufacturer Part Number: ZLF645S2864GP0001
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645S2864GP0001

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 2 V to 3.6 V
• Interface Type: UART
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• Processor Series: ZLF645
• Program Memory Type: Flash

Table 30. ICP Status Register (ICPSTAT)
19-4572; Rev 0; 4/09
Bits
Field
Reset
R/W
Bit Position
[7] 
[6]
[5]
[4]
[3]
[2:0]
ICP Status Register
FLASHCTL FLPROT1
The ICP Status register (see
the ICP and the device.
R
7
0
Value
—
—
0
1
1
0
1
0
1
0
Description
FLASHCTL —When read, this bit indicates whether the device is in FLASH
CONTROL mode.
The device is operating in NORMAL mode.
The device is in FLASH CONTROL mode.
FLPROT1 —When read, this bit indicates the value of the devices FLPROT1
option bit as read from the
on page 175.
FLPROT1 mode is enabled.
FLPROT1 mode is disabled.
FLRWP —When read, this bit indicates the value of the devices FLRWP
option bit as read from the User Option Byte 1 shadow register.
FLRWP mode is enabled.
FLRWP mode is disabled.
Reserved —Must be written to 1.
FLWAIT —When read, this bit indicates whether an ICP initiated Flash
program, page erase, or mass erase operation is completed or not.
An initiated Flash programming, page erase, or mass erase operation is now
complete.
A Flash programming, page erase, or mass erase operation is still in
progress and has not yet completed. No new Flash operations must be
started until this bit reads as a 0.
Reserved —Must be written to 1.
R
6
0
FLRWP
R
5
0
Table
Reserved
30) reports status information about the current state of
R
4
0
User Option Byte 1 Shadow Register (OPT1SR)
In-Circuit Programming Control Register Definitions
FLWAIT
R
3
0
ZLF645 Series Flash MCUs
R
2
0
Product Specification
Reserved
R
1
0
R
0
0
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