Si52147-EVB Silicon Labs, Si52147-EVB Datasheet - Page 4

• Manufacturer Part Number: Si52147-EVB
• Description: Clock & Timer Development Tools 9 PCIe GENERATOR
• Manufacturer: Silicon Labs
• Type: Clock Generatorsr

Specifications of Si52147-EVB

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: Si52147
• Frequency: 100 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: I2C, PCIe

Si52147-EVB
1.1. Generating DIFF Outputs from the Si52147
Upon power-on of the device, if the input pins are left floating, by default all DIFF outputs DIFF[0:8] are ON with
100 MHz and with spread spectrum disabled. The input pin headers have clear indication of jumper settings for
setting logic low (0) and high (1) as shown below, the jumper placed on middle and left pin will set input OE0 to
LOw; and jumper placed on middle and right pin will set input OE0 to high.
The output enable pins can be changed on the fly to observe outputs stopped cleanly. To enable the spread
spectrum, the SSON input needs to change from a logic level low to high. Input functionality is explained in detail
below.
1.1.1. SSON Input
Apply the appropriate logic level to SSON input to achieve clock frequency selection. When the SSON is high,
–0.5% down spread is enabled on all differential outputs with a saw-tooth spread profile. When the SSON is low,
spread profile is disabled.
1.1.2. OE [0:8] Input
The output enable pins can change on the fly when the device is on. Deasserting (valid low) results in
corresponding DIFF output to be stopped after their next transition with final state low/low. Asserting (valid high)
results in corresponding output that was stopped are to resume normal operation in a glitch-free manner.
Each of the hardware OE [0:8] pins are mapped via I
Register Control Bit both need to be high to enable the output. Both of these form an “AND” function to disable or
enable the DIFF output. The DIFF outputs and their corresponding I
Table 3.
4
I
2
C Control Bit
Byte1 [bit 4]
Byte1 [bit 2]
Byte2 [bit 1]
Byte2 [bit 0]
Byte1 [bit 7]
Byte1 [bit 6]
Byte2 [bit 5]
Byte2 [bit 4]
Byte2 [bit 3]
Table 3. Output Enable Control
Output
DIFF0
DIFF1
DIFF2
DIFF3
DIFF4
DIFF5
DIFF6
DIFF7
DIFF8
2
Rev. 0.1
C to control bit in Control register. The hardware pin and the
2
C control bits and hardware pins are listed in
Hardware Control Input
OE4/5
OE4/5
OE6/8
OE6/8
OE6/8
OE0
OE1
OE2
OE3