Si53154-EVB Silicon Labs, Si53154-EVB Datasheet - Page 3

• Manufacturer Part Number: Si53154-EVB
• Description: Clock & Timer Development Tools 4 PCIe BUFFER
• Manufacturer: Silicon Labs
• Type: Clock Buffersr

Specifications of Si53154-EVB

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: Si53154
• Frequency: 100 MHz to 210 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: I2C, PCIe

1.1. Generating DIFF Outputs from the Si53154
Upon power-on of the device if the differential input is applied and input pins are left floating, by default all DIFF
outputs DIFF[0:3] are ON. The input pin headers have clear indication of jumper settings for setting logic low (0)
and high (1) as shown in the figure below, the jumper placed on middle and left pin will set input OE0 to low; and
jumper placed on middle and right pin will set input OE0 to high.
The output enable pins can be changed on the fly to observe outputs stopped cleanly. Input functionality is
explained in detail below.
1.1.1. OE [0:3] Inputs
The output enable pins can change on the fly when the device is on. Deasserting (valid low) results in
corresponding DIFF output to be stopped after their next transition with final state low/low. Asserting (valid high)
results in corresponding output that was stopped are to resume normal operation in a glitch-free manner.
Each of the hardware OE [0:3] pins are mapped via I
Register Control Bit both need to be high to enable the output. Both of these form an “AND” function to disable or
enable the DIFF output. Both of these form an “AND” function to disable or enable the DIFF output. The DIFF
outputs and their corresponding I
I
2
C Control Bit
Byte1 [bit 2]
Byte1 [bit 0]
Byte2 [bit 7]
Byte2 [bit 6]
2
C control bits and hardware pins are listed in Table 2.
Table 2. Output Enable Control
Output
DIFF0
DIFF1
DIFF2
DIFF3
2
Rev. 0.1
C to control bit in Control register. The hardware pin and the
Hardware Control Input
Si53154-EVB
OE0
OE1
OE2
OE3
3