EVAL-AD5222SDZ Analog Devices, EVAL-AD5222SDZ Datasheet - Page 8

• Manufacturer Part Number: EVAL-AD5222SDZ
• Description: Digital Potentiometer Development Tools EVALUATION BOARD
• Manufacturer: Analog Devices
• Series: AD5222r

Specifications of EVAL-AD5222SDZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD5222
• Resistance: 10 kOhms/50 kOhms/100 kOhms/1 MOhms
• Operating Supply Voltage: 5.4 V
• Interface Type: Up/Down
• Maximum Operating Temperature: + 85 C
• Factory Pack Quantity: 1
• For Use With: Sim DAC Web Tool

OPERATION
The AD5222 provides a 128-position, digitally-controlled, variable
resistor (VR) device. Changing the VR settings is accomplished
by pulsing the CLK pin while CS is active low. The U/D (UP/
DOWN) control input pin controls the direction of the increment.
When the wiper hits the end of the resistor (Terminal A or B)
additional CLK pulses no longer change the wiper setting. The
wiper position is immediately decoded by the wiper decode logic
changing the wiper resistance. Appropriate debounce circuitry is
required when push-button switches are used to control the
count sequence and direction of count. The exact timing require-
ments are shown in Figure 2. The AD5222 powers ON in a
centered wiper position, exhibiting nearly equal resistances of
R
DIGITAL INTERFACING OPERATION
The AD5222 contains a push-button controllable interface. The
active inputs are clock (CLK), CS and up/down (U/D). While
the MODE, and DACSEL pins control common updates or
individual updates. The negative-edge sensitive CLK input
requires clean transitions to avoid clocking multiple pulses into
the internal UP/DOWN counter register, Figure 30. Standard
logic families work well. If mechanical switches are used for
product evaluation a flip-flop or other suitable means should
debounce them. When CS is taken active low, the clock begins
to increment or decrement the internal up/down counter, depen-
dent upon the state of the U/D control pin. The UP/DOWN
counter value (D) starts at 40
CLK pulse will increment the value of the internal counter by
1 LSB until the full-scale value of 7F
U/D pin is logic high. If the U/D pin is taken to logic low, the
counter will count down, stopping at code 00
Additional clock pulses on the CLK pin are ignored when the
wiper is at either the 00
detailed digital logic interface circuitry is shown in Figure 30.
AD5222
WA
DACSEL
and R
MODE
GND
CLK
V
U/D
CS
DD
WB
.
AD5222
ENABLE
SELECT
POR
DAC
AND
Figure 29. Block Diagram
H
position or the 7F
COUNTER
COUNTER
UP/DOWN
UP/DOWN
H
at system power ON. Each new
H
is reached, as long as the
DECODE
DECODE
H
position. The
H
(zero-scale).
A1
W1
B1
A2
W2
B2
V
SS
–8–
All digital inputs (CS, U/D, CLK, MODE, DACSEL) are
protected with a series input resistor and parallel Zener ESD
structure shown in Figure 31. All potentiometer terminal pins
(A, B, W) are protected from ESD as shown in Figure 32.
Figure 32. Equivalent ESD Protection Analog Pins
Figure 31. Equivalent ESD Protection Digital Pins
Figure 30. Detailed Digital Logic Interface Circuit
DACSEL
Figure 33. AD5222 Equivalent RDAC Circuit
MODE
CLK
U/D
CS
UP/DOWN
DECODE
RDAC
CNTR
D0
D1
D2
D3
D4
D5
D6
&
A, B, W
V
SS
V
SS
1k
R
R
R
R
R
S
S
S
S
S
20
= R
NOMINAL
LOGIC
/128
A
W
B
COUNTER
COUNTER
RDAC 1
RDAC 2
U/D
U/D
REV. 0