AT25DF641-MWH-Y Atmel, AT25DF641-MWH-Y Datasheet - Page 45

• Manufacturer Part Number: AT25DF641-MWH-Y
• Description: IC FLASH 64MBIT 100MHZ 8VDFN
• Manufacturer: Atmel

Specifications of AT25DF641-MWH-Y

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VDFN
• Architecture: Sectored
• Interface Type: SPI Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 19 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 128
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 5ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VDFN
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5.
3680F–DFLASH–4/10
Hold
The
sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a
program or erase cycle. Therefore, if an erase cycle is in progress, asserting the
operation, and the erase cycle will continue until it is finished.
The Hold mode can only be entered while the
the
mode won’t be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as
long as the
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin
will be ignored. The
To end the Hold mode and resume serial communication, the
pulse. If the
of the next SCK low pulse.
If the
be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.
Figure 11-5. Hold Mode
HOLD
SCK
CS
HOLD
HOLD
CS
pin is deasserted while the
pin during the SCK low pulse. If the
pin is used to pause the serial communication with the device without having to stop or reset the clock
HOLD
HOLD
pin and
pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning
WP
pin, however, can still be asserted or deasserted while in the Hold mode.
CS
pin are asserted.
HOLD
Hold
pin is still asserted, then any operation that may have been started will
CS
HOLD
pin is asserted. The Hold mode is activated simply by asserting
pin is asserted during the SCK high pulse, then the Hold
HOLD
Hold
pin must be deasserted during the SCK low
Atmel AT25DF641
HOLD
Hold
pin will not pause the
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