NetduinoPlus2 Netduino, NetduinoPlus2 Datasheet - Page 114

• Manufacturer Part Number: NetduinoPlus2
• Description: Development Boards & Kits - ARM NETDUINO PLUS 2
• Manufacturer: Netduino

Specifications of NetduinoPlus2

• Rohs: yes
• Product: Development Boards
• Tool Is For Evaluation Of: STM32F405RG
• Core: ARM Cortex M4
• Interface Type: I2C, SPI, UART, USB
• Operating Supply Voltage: 7.5 v to 9 V
• Data Bus Width: 32 bit
• Description/function: Arduino form factor
• Dimensions: 2.8 in x 2.1 in
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C

Electrical characteristics
114/180
I
Unless otherwise specified, the parameters given in
are derived from tests performed under the ambient temperature, f
supply voltage conditions summarized in
Refer to
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I
Table 54.
1. Remapped SPI1 characteristics to be determined.
2. TBD stands for “to be defined”.
3. Based on characterization, not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
2
DuCy(SCK)
t
t
t
dis(SO)
t
S - SPI interface characteristics
t
t
t
w(SCLH)
v(SO)
t
w(SCLL)
a(SO)
v(MO)
1/t
su(NSS)
t
Symbol
t
h(NSS)
t
t
t
su(MI)
t
h(MO)
the data.
the data in Hi-Z
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCL)
f
f(SCL)
c(SCK)
SCK
(3)(4)
(3)(1)
(3)(1)
(3)
(3)(5)
(3)
(3)
(3)
(3)
(3)
(3)
Section 5.3.16: I/O port characteristics
(3)
(3)
(3)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock
duty cycle
NSS setup time
NSS hold time
SCK high and low time Master mode, f
Data input setup time
Data input hold time
Data output access
time
Data output disable
time
Data output valid time Slave mode (after enable edge)
Data output valid time Master mode (after enable edge)
Data output hold time
Parameter
Doc ID 022152 Rev 3
(1)(2)
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Table
Conditions
13.
for more details on the input/output alternate
PCLK
PCLK
= 20 MHz
Table 54
= TBD MHz
STM32F405xx, STM32F407xx
for SPI or in
PCLKx
4t
2t
TBD
Min
PCLK
PCLK
30
15
5
5
5
4
2
2
-
-
-
-
-
0
frequency and V
Table 55
3 t
TBD
Max
37.5
37.5
70
10
25
2
PCLK
-
-
-
8
-
-
-
-
5
-
S).
for I
MHz
Unit
ns
ns
%
2
S
DD