NetduinoPlus2 Netduino, NetduinoPlus2 Datasheet - Page 175

• Manufacturer Part Number: NetduinoPlus2
• Description: Development Boards & Kits - ARM NETDUINO PLUS 2
• Manufacturer: Netduino

Specifications of NetduinoPlus2

• Rohs: yes
• Product: Development Boards
• Tool Is For Evaluation Of: STM32F405RG
• Core: ARM Cortex M4
• Interface Type: I2C, SPI, UART, USB
• Operating Supply Voltage: 7.5 v to 9 V
• Data Bus Width: 32 bit
• Description/function: Arduino form factor
• Dimensions: 2.8 in x 2.1 in
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C

STM32F405xx, STM32F407xx
8
Revision history
Table 97.
15-Sep-2011
24-Jan-2012
Date
Document revision history
Revision
1
2
Initial release.
Added WLCSP90 package on cover page.
Renamed USART4 and USART5 into UART4 and UART5, respectively.
Updated number of USB OTG HS and FS in
and STM32F407xx: features and peripheral
Updated
STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package
Figure 4: Compatible board design between STM32F2xx and
STM32F4xx for LQFP176
Updated
Modified I/Os used to
USB OTG FS in
Updated note in
PDR_ON no more available on LQFP100 package. Updated
Section 2.2.16: Voltage
minimum supply voltage of 1.7 V in the whole document.
Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for
UART4 and UART5 in
Removed support of I2C for OTG PHY in
serial bus on-the-go full-speed
Added
Table 6: STM32F40x pin and ball
and V
definitions
versus additional functions; signal corresponding to LQFP100 pin 99
changed from PDR_ON to V
alternate functions for all I/Os; ADC3_IN8 added as alternate function
for PF10; FSMC_CLE and FSMC_ALE added as alternate functions for
PD11 and PD12, respectively; PH10 alternate function
TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PA5 I/O
structure to TTa.
Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in
STM32F40x pin and ball definitions
mapping.
Changed TCM data RAM to CCM data RAM in
memory
Added I
characteristics.
Added
operating
Updated
supply
Doc ID 022152 Rev 3
SS
Table 5: Legend/abbreviations used in the pinout
Note 1
range.
VDD
_8 by V
map.
Figure 3: Compatible board design between
Section 2.2.9: Flexible static memory controller
Table 14: Limitations depending on the operating power
conditions, and added maximum power dissipation values.
to better highlight I/O structure, and alternate functions
and I
related to f
SS
Section 2.2.13: Boot
Section 2.2.14: Power supply
VSS
; reformatted
maximum values in
reprogram the Flash memory for
Table 4: USART feature
regulator. Updated condition to obtain a
HCLK
package, and removed note 1 and 2.
SS
, updated
Changes
; EVENTOUT added in the list of
(OTG_FS).
Table 6: STM32F40x pin and ball
definitions: replaced V
and
modes.
Note 2
Table 8: Alternate function
Table 11: Current
Section 2.2.29: Universal
counts.
Table 2: STM32F405xx
schemes.
comparison.
Figure 16: STM32F40x
in
Table 13: General
Revision history
SS
table.
(FSMC).
_3, V
CAN2 and
Table 6:
and
175/180
SS
_4,