NetduinoPlus2 Netduino, NetduinoPlus2 Datasheet - Page 35

• Manufacturer Part Number: NetduinoPlus2
• Description: Development Boards & Kits - ARM NETDUINO PLUS 2
• Manufacturer: Netduino

Specifications of NetduinoPlus2

• Rohs: yes
• Product: Development Boards
• Tool Is For Evaluation Of: STM32F405RG
• Core: ARM Cortex M4
• Interface Type: I2C, SPI, UART, USB
• Operating Supply Voltage: 7.5 v to 9 V
• Data Bus Width: 32 bit
• Description/function: Arduino form factor
• Dimensions: 2.8 in x 2.1 in
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C

STM32F405xx, STM32F407xx
2.2.31
2.2.32
2.2.33
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator.
The major features are:
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Digital camera interface (DCMI)
The camera interface is not available in STM32F405xx devices.
STM32F407xx products embed a camera interface that can connect with camera modules
and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The
camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
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Random number generator (RNG)
All STM32F405xx and STM32F407xx products embed an RNG that delivers 32-bit random
numbers generated by an integrated analog circuit.
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 84 MHz.
Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
6 bidirectional endpoints
12 host channels with periodic OUT support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image
Doc ID 022152 Rev 3
Description
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