MAX98089EVKIT+WLP Maxim Integrated, MAX98089EVKIT+WLP Datasheet - Page 119

• Manufacturer Part Number: MAX98089EVKIT+WLP
• Description: Audio IC Development Tools
• Manufacturer: Maxim Integrated
• Type: Audio CODECr

Specifications of MAX98089EVKIT+WLP

• Product: Evaluation Kits
• Tool Is For Evaluation Of: MAX98089
• Operating Supply Voltage: 2.8 V to 5.5 V
• Interface Type: I2C
• Operating Supply Current: 1 A

The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
IC, the seven most significant bits are 0010000. Setting
the read/write bit to 1 (slave address = 0x21) configures
the IC for read mode. Setting the read/write bit to 0 (slave
address = 0x20) configures the ICs for write mode. The
address is the first byte of information sent to the IC after
the START condition.
The acknowledge bit (ACK) is a clocked 9th bit that the
IC uses to handshake receipt each byte of data when
in write mode (Figure 35). The IC pulls down SDA dur-
ing the entire master-generated 9th clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
Figure 35. Acknowledge
Figure 36. Writing One Byte of Data to the ICs
Figure 37. Writing n-Bytes of Data to the ICs
Maxim Integrated
S
ACKNOWLEDGE FROM MAX98089
S
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX98089
SLAVE ADDRESS
R/W
O
SCL
SDA
A
CONDITION
ACKNOWLEDGE FROM MAX98089
START
R/W
REGISTER ADDRESS
O
A
Slave Address
Acknowledge
Low-Power, Stereo Audio Codec
1
ACKNOWLEDGE FROM MAX98089
REGISTER ADDRESS
2
with FlexSound Technology
A
ACKNOWLEDGE FROM MAX98089
B7 B6 B5 B4 B3 B2 B1 B0
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
NOT ACKNOWLEDGE
is busy or if a system fault has occurred. In the event
of an unsuccessful data transfer, the bus master retries
communication. The master pulls down SDA during the
9th clock cycle to acknowledge receipt of data when the
IC is in read mode. An acknowledge is sent by the master
after each read byte to allow data transfer to continue. A
not acknowledge is sent when the master reads the final
byte of data from the IC, followed by a STOP condition.
A write to the IC includes transmission of a START condi-
tion, the slave address with the R/W bit set to 0, one byte
of data to configure the internal register address pointer,
one or more bytes of data, and a STOP condition. Figure
36 illustrates the proper frame format for writing one byte
of data to the IC. Figure 37 illustrates the frame format for
writing n-bytes of data to the IC.
DATA BYTE 1
ACKNOWLEDGE
1 BYTE
8
ACKNOWLEDGMENT
CLOCK PULSE FOR
A
9
B7
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
A
B6
ACKNOWLEDGE FROM MAX98089
B5
ACKNOWLEDGE FROM MAX98089
DATA BYTE
B4
B7 B6 B5 B4 B3 B2 B1 B0
1 BYTE
B3
MAX98089
DATA BYTE n
B2
1 BYTE
B1
Write Data Format
B0
A
P
A
P
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