MAX98089EVKIT+WLP Maxim Integrated, MAX98089EVKIT+WLP Datasheet - Page 58

• Manufacturer Part Number: MAX98089EVKIT+WLP
• Description: Audio IC Development Tools
• Manufacturer: Maxim Integrated
• Type: Audio CODECr

Specifications of MAX98089EVKIT+WLP

• Product: Evaluation Kits
• Tool Is For Evaluation Of: MAX98089
• Operating Supply Voltage: 2.8 V to 5.5 V
• Interface Type: I2C
• Operating Supply Current: 1 A

Maxim Integrated
BUMP
(WLP)
E1
E2
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
(TQFN-EP)
PIN
56
45
37
40
38
52
51
49
44
41
39
6
5
9
3
2
4
DIGMICDATA
DIGMICCLK
JACKSNS
EXTMICN
LRCLKS2
EXTMICP
DVDDS1
MICBIAS
BCLKS2
SDINS1
MIC1P/
MIC1N/
NAME
DGND
MCLK
INA2/
INA1/
INB1
REG
SDA
SCL
IRQ
Low-Power, Stereo Audio Codec
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF ca-
pacitor.
Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz.
S1 Digital Audio Serial-Data DAC Input. The input/output voltage is referenced to
DVDDS1.
Hardware Interrupt Output. IRQ can be programmed to pull low when bits in
status register 0x00 change state. Read status register 0x00 to clear IRQ once
set. Repeat faults have no effect on IRQ until it is cleared by reading the I
register 0x00. Connect a 10kI pullup resistor to DVDD for full output swing.
Jack Sense. Detects the insertion and removal of a jack. In typical applications,
connect JACKSNS to the MIC pole of the jack. See the Jack Detection section.
Single-Ended Line Input B1. Also negative differential line input B.
Positive Differential Microphone 1 Input. AC-couple a microphone with a series
1FF capacitor. Can be retasked as a digital microphone data input.
Single-Ended Line Input A2. Also positive differential line input A or negative dif-
ferential external microphone input.
Digital Ground
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave
mode and an output when in master mode. The input/output voltage is referenced
to DVDDS2.
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate
clock and determines whether audio data on S2 is routed to the left or right chan-
nel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an input when the
IC is in slave mode and an output when in master mode. The input/output voltage
is referenced to DVDDS2.
I
swing.
I
Common-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor.
Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external 2.2kI resis-
tor should be placed between MICBIAS and the microphone output.
Negative Differential Microphone 1 Input. AC-couple a microphone with a series
1FF capacitor. Can be retasked as a digital microphone clock output.
Single-Ended Line Input A1. Also negative differential line input A or positive dif-
ferential external microphone input.
2
2
C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output
C Serial-Clock Input. Connect a pullup resistor to DVDD for full output swing.
with FlexSound Technology
Bump/Pin Description (continued)
FUNCTION
MAX98089
2
C status
58