MIKROE-957 mikroElektronika, MIKROE-957 Datasheet - Page 44

• Manufacturer Part Number: MIKROE-957
• Description: Other Development Tools ASLK PRO ANALOG DEVELOPMENT SYSTEM
• Manufacturer: mikroElektronika

Specifications of MIKROE-957

• Rohs: yes
• Product: Analog System Lab Kit PRO
• Tool Is For Evaluation Of: TL082, MPY634
• Operating Supply Voltage: 2.5 V to 5.5 V
• Description/function: Analog Lab Kit for Undergraduate Engineering
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C

In the loop of self-tuned filter studied in experiment number 5 if we replace the
Voltage Control Filter (VCF) with Voltage Control Oscillator (VCO) (discussed in
experiment 6) then it becomes PLL as shown in Figure 7.1. The reader will benefit
from viewing the recorded lecture at [22].
The sensitivity of the PLL is given by K
frequency of oscillation of VCO. Hence
page 44
7.1 Brief theory and motivation
The goal of this experiment is to make you aware of the functionality of
the Phase Lock Loop commonly referred to as PLL which is primarily used
for a frequency synthesizer in high frequency stable clock generators. From
a crystal of some kHz range, it is possible to generate waveform of GHz
frequency range using a PLL.
Figure 7.1: Phase Locked Loop (PLL) and its characteristics
Goal of the experiment
VCO
(Output)
V
Input Frequency
O
W(Input)
V
~
~
~
V
V
V
V
K
K
K
d
dV
d
dV
Vc Control Voltage
I
CQ
0
i
ref
~
~
VCO
VCO
0
pd
=
Q
c
c
V
~
~
~
V
V
V
V
K
K
#
d
dV
d
dV
K
~
~
K
~
V
V
V
V
K
d
dV
d
dV
=
CQ
0
i
ref
~
c
~
VCO
CQ
VCO
0
0
i
=
ref
pd
~
~
VCO
VCO
0
Q
R
=
pd
4
c
c
=
Q
V
c
c
#
V
r
2
=
c
#
V RC
=
=
and is equal to
c
4
V RC
=
4
~
r
2
r
r
V RC
2
V RC
V RC
V
r
~
#
V RC
r
~
$
V
r
#
r
V
V
$
r
$
#
c
$
V
$
c
$
c
V
V
A
c
A
c
V
c
V
A
C
c
0
c
0
c
0
#
#
Vref=0
, which is nothing but
#
K
K
VCO
VCO
K
VCO
~
~
~
V
V
V
V
K
K
K
d
dV
d
dV
CQ
0
i
ref
~
~
VCO
VCO
0
pd
Q
=
c
c
V
#
, where
=
c
=
4
r
2
V RC
V RC
~
r
V
r
#
$
V
$
c
V
A
c
c
0
~
~
~
V
V
V
V
K
K
K
#
d
dV
d
dV
CQ
0
i
ref
VCO
~
~
VCO
0
pd
K
=
Q
c
c
V
K
~
~
K
~
V
V
V
V
K
d
dV
d
dV
#
VCO
=
c
CQ
0
i
=
ref
~
~
VCO
VCO
0
4
pd
Q
=
r
2
c
c
V RC
V
V RC
#
~
=
r
c
V
r
=
#
4
$
(7.1)
V
$
r
c
2
V RC
V RC
A
c
V
~
r
V
r
c
#
0
$
$
V
c
#
,
c
V
A
c
0
K
#
VCO
~
~
When no input voltage is applied to the system, the system oscillates at the free
~
running frequency of the VCO, given by
V
will continue to run at the free running frequency and the phase difference between
V
the two signals
V
of Chapter 6). As the frequency of input signal is changed, the control voltage will
V
change correspondingly, so as to lock the output frequency to the input frequency.
As a result, there is a change of phase difference between the two signals away
7.2 Specifications
Design a PLL to get locked to frequency of 1 kHz.
K
~
K
~
K
~
V
V
K
V
from 90˚. The range of input frequencies for which output frequencies gets locked
V
to the input is called the lock range of the system. The lock range is defined as
K
d
d
dV
dV
d
dV
Figure 7.2: Sample output waveform for the Phase Locked Loop (PLL) Experiment
K
V
CQ
0
i
CQ
ref
0
i
ref
~
VG1
~
VCO
~
0
VCO
VCO
0
pd
pd
G1
VCO
=
=
Q
Q
c
c
c
. If the input is applied to the system with the same frequency as
V
V
#
#
=
=
c
c
=
=
4
4
r
2
r
2
V RC
V RC
V RC
V RC
+
~
~
+
r
r
r
#
V
r
#
$
$
V
$
$
c
c
V
V
A
A
c
c
V
-10.00
10.00
c
c
0
0
-5.00
5.00
0.00
#
#
U4
K
K
U
0.00
VCO
VCO
4
~
~
K
~
V
V
V
V
K
dV
d
dV
+
CQ
0
i
ref
~
R4
VCO
0
pd
R5
on either side of
V2
+
=
Q
c
c
and
V
#
=
c
R
R
V
=
4
4
5
2
r
2
V RC
V RC
~
~
~
~
V
V
V
V
C2
K
K
d
r
dV
V
r
#
V
$
CQ
0
i
ref
~
V
$
VCO
0
F3
c
as 90˚ since
pd
=
Q
c
A
c
V
V
#
c
=
0
c
=
C
VF3
4
#
r
2
U3
2
V RC
U
V RC
~
K
r
3
r
#
$
VCO
V
$
c
10.00m
A
c
V
c
0
~
#
~
~
V
V
V
V
K
K
K
d
dV
d
dV
CQ
0
i
ref
~
~
VCO
VCO
0
pd
K
R
Q
=
c
c
V
.
VCO
#
1
~
~
V
V
V
V
=
R1
K
K
c
d
dV
=
4
CQ
0
i
ref
~
~
~
VCO
0
~
V
V
V
V
K
pd
K
r
2
d
dV
Q
V RC
Time (s)
c
V RC
CQ
0
i
ref
~
V
~
VCO
0
is 0 (already explained in Experiment 5
#
r
pd
Q
V
r
#
=
=
c
c
=
$
V
$
V
c
#
Analog System Lab Kit PRO
=
c
with corresponding control voltage of
r
2
c
V
A
=
4
V RC
~
U
c
0
r
2
r
#
V RC
V RC
#
1
~
V
$
r
V
r
#
+
V
A
-
c
$
K
V
$
c
C
20.00m
c
0
V
A
c
C1
VCO
1
#
c
U1
0
#
K
VCO
K
VCO
V
VF2
F2
R
2
R2
+
30.00m
V1
+
-
R3
~
~
K
~
V
V
V
V
K
U
dV
d
dV
V
CQ
0
i
ref
2
~
1
VCO
0
pd
U2
Q
=
c
c
R
V
, the PLL
#
=
c
3
=
4
r
2
V RC
V RC
~
r
V
r
#
$
VF1
$
V
c
c
V
A
c
0
V
#
F1
K
VCO