IS42S16100E-7TLI ISSI, Integrated Silicon Solution Inc, IS42S16100E-7TLI Datasheet - Page 50
![IC SDRAM 16MBIT 143MHZ 50TSOP](/photos/7/28/72801/is42s16100e-7tli_sml.jpg)
IS42S16100E-7TLI
Manufacturer Part Number
IS42S16100E-7TLI
Description
IC SDRAM 16MBIT 143MHZ 50TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Specifications of IS42S16100E-7TLI
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
16M (1M x 16)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
50-TSOPII
Organization
1Mx16
Density
16Mb
Address Bus
12b
Access Time (max)
6/5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
150mA
Pin Count
50
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
706-1072
IS42S16100E-7TLI
IS42S16100E-7TLI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S16100E-7TLI
Manufacturer:
ISSI
Quantity:
11 200
Company:
Part Number:
IS42S16100E-7TLI
Manufacturer:
ISSI
Quantity:
104
Part Number:
IS42S16100E-7TLI
Manufacturer:
ISSI
Quantity:
20 000
Company:
Part Number:
IS42S16100E-7TLI-TR
Manufacturer:
ISSI
Quantity:
1 000
IS42S16100E, IC42S16100E
Read Cycle / Page Mode; Data Masking
50
Note 1: A8,A9 = Don’t Care.
CAS latency = 2, burst length = 2
A0-A9
DQM
CKE
RAS
CAS
CLK
A10
A11
WE
DQ
CS
t
CKS
t
CS
T0
t
t
t
t
t
t
t
t
CS
CS
CS
AS
AS
t
AS
CKA
CK
CH
BANK 1
BANK 0
<
ROW
ROW
ACT
T1
t
>
CHI
t
t
t
RAS
RC
t
t
RCD
t
t
t
t
AH
AH
CH
CH
CH
AH
T2
t
CL
t
CS
COLUMN m
<
NO PRE
BANK 1
BANK 0
READ
T3
>
(1)
t
t
CAC
QMD
t
LZ
T4
t
AC
COLUMN n
NO PRE
BANK 0
BANK 1
T5
D
OUT
t
OH
(1)
m
t
AC
t
CAC
t
CH
Integrated Silicon Solution, Inc. — www.issi.com
<
NO PRE
MASK
T6
D
OUT
>
t
OH
m+1
t
t
HZ
AC
<
<
READA, ENB
READ, ENB
AUTO PRE
COLUMN o
NO PRE
BANK 1
BANK 0
T7
D
OUT
t
(1)
OH
t
n
>
QMD
>
t
CAC
t
LZ
T8
t
AC
BANK 0 AND 1
BANK 0 OR 1
<
<
BANK 0
BANK 1
PALL
PRE
T9
D
OUT
>
>
t
OH
t
t
o
RQL
RP
t
AC
T10
D
Undefined
Don't Care
OUT
t
OH
o+1
t
HZ
01/22/08
Rev. C