IS42S16400F-5BL ISSI, Integrated Silicon Solution Inc, IS42S16400F-5BL Datasheet - Page 5

• Manufacturer Part Number: IS42S16400F-5BL
• Description: IC SDRAM 64MBIT 200MHZ 54BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16400F-5BL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-BGA
• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5ns
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S16400F
IS45S16400F
PIN FUNCTIONS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
07/28/2010
BA0, BA1
Symbol
A0-A11
DQ0 to
LDQM,
UDQM
GNd
DQ15
V
GNd
CAS
CKE
RAS
CLK
WE
V
CS
ddq
dd
q
11,13, 42, 44, 45,
47, 48, 50, 51, 53
TSOP Pin No.
2, 4, 5, 7, 8, 10,
6, 12, 46, 52
3, 9, 43, 49
28, 41, 54
1, 14, 27
23 to 26
29 to 34
22, 35
20, 21
15, 39
17
37
38
19
18
16
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
DQ Pin
Type
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to deter-
mine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs
go to the HIGH impedance state when LDQM/UDQM is HIGH. This function cor-
responds to OE in conventional DRAMs. In write mode, LDQM and UDQM control
the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is en-
abled, and data can be written to the device. When LDQM or UDQM is HIGH, input
data is masked and cannot be written to the device.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
V
V
GNd
GNd is the device internal ground.
ddq
dd
is the device internal power supply.
q
is the output buffer power supply.
is the output buffer ground.
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