IS61LV5128AL-10KLI ISSI, Integrated Silicon Solution Inc, IS61LV5128AL-10KLI Datasheet - Page 8

• Manufacturer Part Number: IS61LV5128AL-10KLI
• Description: IC SRAM 4MBIT 10NS 36SOJ
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LV5128AL-10KLI

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (512K x 8)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 36-SOJ
• Density: 4Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: SOJ
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 95mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 36
• Word Size: 8b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITE CYCLE NO. 3
IS61LV5128AL
WRITE CYCLE NO. 2
8
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
2. I/O will assume the High-Z state if OE > V
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
ADDRESS
ADDRESS
D
D
OUT
OUT
WE
WE
D
D
OE
OE
CE
CE
IN
IN
LOW
LOW
LOW
t
SA
(1,2)
(WE Controlled: OE is LOW During Write Cycle)
t
DATA UNDEFINED
DATA UNDEFINED
SA
(WE Controlled: OE is HIGH During Write Cycle)
IH
.
Integrated Silicon Solution, Inc. — www.issi.com —
VALID ADDRESS
t
t
t
t
AW
AW
HZWE
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
WC
HIGH-Z
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
CE_WR2.eps
ISSI
CE_WR3.eps
1-800-379-4774
04/15/05
Rev. C
®