IS42S32200E-7B-TR ISSI, Integrated Silicon Solution Inc, IS42S32200E-7B-TR Datasheet - Page 17
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IS42S32200E-7B-TR
Manufacturer Part Number
IS42S32200E-7B-TR
Description
IC SDRAM 64MBIT 143MHZ 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Specifications of IS42S32200E-7B-TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-BGA
Organization
2Mx32
Density
64Mb
Address Bus
13b
Access Time (max)
8/5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
140mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
IS42S32200E, IS45S32200E
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated
(see Activating Specific Row Within Specific Bank).
After opening a row (issuing an ACTIVE command), a READ
or WRITE command may be issued to that row, subject to
the t
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. For example, a t
125 MHz clock (8ns period) results in 2.5 clocks, rounded
to 3. This is reflected in the following example, which cov-
ers any case where 2 < [t
procedure is used to convert other specification limits from
time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is defined by t
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead.The minimum
time interval between successive ACTIVE commands to
different banks is defined by t
Example: Meeting t
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/12/2010
rcd
specification. Minimum t
COMMAND
RCD
rcd
rc
rcd
.
specification of 20ns with a
rrd
(MIN) when 2 < [t
CLK
(MIN)/t
rcd
.
should be divided by
ck
ACTIVE
] ≤ 3. (The same
T0
RCD
t
NOP
RCD
T1
(min)/t
Activating Specific Row Within Specific Bank
BA0, BA1
CK
A0-A10
NOP
T2
] ≤ 3
CKE
RAS
CAS
CLK
WE
CS
HIGH
READ or
WRITE
T3
DON'T CARE
BANK ADDRESS
ROW ADDRESS
T4
17