EVAL-ADM1276EBZ Analog Devices, EVAL-ADM1276EBZ Datasheet - Page 24

• Manufacturer Part Number: EVAL-ADM1276EBZ
• Description: Power Management IC Development Tools EVALUATION BOARD
• Manufacturer: Analog Devices
• Type: Hot Swap & Power Distributionr
• Series: ADM1276r

Specifications of EVAL-ADM1276EBZ

• Rohs: yes
• Tool Is For Evaluation Of: ADM1276
• Input Voltage: 20 V
• Factory Pack Quantity: 1

ADM1276
PMBus INTERFACE
The I
to communicate. It defines the electrical specifications, the bus
timing, the physical layer, and some basic protocol rules.
SMBus is based on I
fault tolerant bus. Functions such as bus timeout and packet
error checking are added to help achieve this robustness, along
with more specific definitions of the bus messages used to read
and write data to devices on the bus.
PMBus is layered on top of SMBus and, in turn, on I
SMBus defined bus messages, PMBus defines a set of standard
commands that can be used to control a device that is part of a
power chain.
The ADM1276 command set is based upon the PMBus™ Power
System Management Protocol Specification, Part I and Part II,
Revision 1.2. This version of the standard is intended to provide
a common set of commands for communicating with dc-to-dc
type devices. However, many of the standard PMBus commands
can be mapped directly to the functions of a hot swap controller.
Part I and Part II of the PMBus standard describe the basic
commands and how they can be used in a typical PMBus setup.
The following sections describe how the PMBus standard and
the ADM1276 specific commands are used.
DEVICE ADDRESSING
The ADM1276 is available in one model: the ADM1276-3. The
PMBus address is 7 bits in size. The upper 5 bits (MSBs) of the
address word are fixed. The base address for the ADM1276 is
01000xx (0x20).
The ADM1276 has a single ADR pin that is used to select one of
four possible addresses. The ADR pin connection selects the
lowest two bits (LSBs) of the 7-bit address word (see Table 6).
Table 6. PMBus Addresses and ADR Pin Connection
Value of Address LSBs
00
01
10
11
SMBus PROTOCOL USAGE
All I
defined bus protocols. The following SMBus protocols are
implemented by the ADM1276:
•
•
•
•
•
•
•
2
Send byte
Receive byte
Write byte
Read byte
Write word
Read word
Block read
C transactions on the ADM1276 are done using SMBus
2
C bus is a common, simple serial bus used by many devices
2
C and aims to provide a more robust and
ADR Pin Connection
Connect to GND
150 kΩ resistor to GND
No connection (floating)
Connect to VCAP
2
C. Using the
Rev. B | Page 24 of 48
PACKET ERROR CHECKING
The ADM1276 PMBus interface supports the use of the packet
error checking (PEC) byte that is defined in the SMBus standard.
The PEC byte is transmitted by the ADM1276 during a read
transaction or sent by the bus host to the ADM1276 during a
write transaction. The ADM1276 supports the use of PEC with
all the SMBus protocols that it implements.
The use of the PEC byte is optional. The bus host can decide
whether to use the PEC byte with the ADM1276 on a message-
by-message basis. There is no need to enable or disable PEC in
the ADM1276.
The PEC byte is used by the bus host or the ADM1276 to detect
errors during a bus transaction, depending on whether the trans-
action is a read or a write. If the host determines that the PEC
byte read during a read transaction is incorrect, it can decide to
repeat the read if necessary. If the ADM1276 determines that the
PEC byte sent during a write transaction is incorrect, it ignores
the command (does not execute it) and sets a status flag.
Within a group command, the host can choose to send or not
send a PEC byte as part of the message to the ADM1276.
PARTIAL TRANSACTIONS ON I
In the event of a specific sequence of events occurring on the
I
into a state where it will fail to acknowledge the next I
transaction directed to it. There are two ways that this behavior
can be triggered:
•
•
In the event that the device does not acknowledge a transaction,
then the I
series of up to 16 SCL clock pulses, or performing a dummy
transaction to another I
2
C bus, it is possible for the I
A partial I
followed by a single SCL clock pulse and stop condition.
If the I
hold time when signaling the ACK/NACK bit at the end of
a transaction. The device sees this as a single SCL clock
partial transaction.
2
C interface on the device can be reset by sending a
2
C bus master does not follow the 300 ns SDA data
2
C transaction consisting of a start condition,
2
C address on the bus.
2
C interface on the device to go
2
C BUS
Data Sheet
2
C