IS42S16800D-7BI ISSI, Integrated Silicon Solution Inc, IS42S16800D-7BI Datasheet - Page 26
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IS42S16800D-7BI
Manufacturer Part Number
IS42S16800D-7BI
Description
IC SDRAM 128MBIT 143MHZ 54BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S16800D-7TL.pdf
(62 pages)
Specifications of IS42S16800D-7BI
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (8Mx16)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-BGA
Density
128Mb
Address Bus
14b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
CAS LATENCY
IS42S81600D,
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n + m. The DQs will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant
access times are met, the data will be valid by clock edge
n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ
command is registered at T0 and the latency is programmed
to two clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in CAS Latency diagrams. The
Allowable Operating Frequency table indicates the operat-
ing frequencies at which each CAS latency setting can be
used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
26
IS42S16800D
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CAS Latency - 2
NOP
NOP
CAS Latency - 3
T1
T1
t
LZ
t
AC
CAS Latency
Operating Mode
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
Speed
-75E
NOP
NOP
Allowable Operating Frequency (MHz)
T2
T2
-6
-7
Integrated Silicon Solution, Inc. — www.issi.com
D
OUT
t
t
OH
LZ
t
AC
NOP
CAS Latency = 2
T3
T3
D
DON'T CARE
UNDEFINED
OUT
t
OH
125
100
133
T4
CAS Latency = 3
166
143
—
07/28/08
Rev. E