IS42S16160D-75EBL ISSI, Integrated Silicon Solution Inc, IS42S16160D-75EBL Datasheet - Page 50

• Manufacturer Part Number: IS42S16160D-75EBL
• Description: IC SDRAM 256MBIT 133MHZ 54BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S16160D-75EBL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S83200D, IS42S16160D
IS45S83200D, IS45S16160D
50
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
the programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9
= 0).
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
READ With Auto Precharge interrupted by a READ
READ With Auto Precharge interrupted by a WRITE
Internal States
COMMAND
ADDRESS
BANK m
BANK n
Internal States
COMMAND
ADDRESS
CLK
DQ
BANK m
BANK n
DQM
CLK
DQ
T0
Page Active
NOP
READ - AP
BANK n,
T0
BANK n
COL a
Page Active
CAS Latency - 3 (BANK n)
BANK n,
READ - AP
COL a
BANK n
T1
Page Active
READ with Burst of 4
T1
NOP
Page Active
READ with Burst of 4
CAS Latency - 3 (BANK n)
T2
NOP
T2
NOP
BANK n,
READ - AP
COL b
BANK m
T3
T3
NOP
D
OUT
CAS Latency - 3 (BANK m)
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
2.Interrupted by a WRITE (with or without auto precharge):
a
Interrupt Burst, Precharge
A READ to bank m will interrupt a READ on bank n,
CAS latency later. The PRECHARGE to bank n will
begin when the READ to bank m is registered.
A WRITE to bank m will interrupt a READ on bank n
when registered.DQM should be used three clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
WRITE - AP
Integrated Silicon Solution, Inc. — www.issi.com
T4
NOP
BANK m,
BANK m
T4
D
COL b
D
t
OUT
RP - BANK n
IN
READ with Burst of 4
b
a
Interrupt Burst, Precharge
WRITE with Burst of 4
T5
T5
D
NOP
D
NOP
IN
OUT
t
RP - BANK n
b+1
a+1
T6
D
NOP
T6
NOP
IN
D
b+2
OUT
b
DON'T CARE
T7
DON'T CARE
D
NOP
Idle
T7
Write-Back
IN
NOP
D
b+3
Precharge
OUT
t
DPL - BANK m
t
Idle
RP - BANK m
b+1
04/05/2010
Rev. D