IS42S32400D-6B ISSI, Integrated Silicon Solution Inc, IS42S32400D-6B Datasheet - Page 44
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IS42S32400D-6B
Manufacturer Part Number
IS42S32400D-6B
Description
IC SDRAM 128MBIT 166MHZ 90FBGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S32400D-7TL.pdf
(60 pages)
Specifications of IS42S32400D-6B
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-FBGA
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
Mini BGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32400D-6B
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Company:
Part Number:
IS42S32400D-6B-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Company:
Part Number:
IS42S32400D-6BL
Manufacturer:
DALLAS
Quantity:
49
Part Number:
IS42S32400D-6BL
Manufacturer:
ICSI
Quantity:
20 000
IS42S32400D
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
44
COMMAND
INTERNAL
ADDRESS
CLOCK
INTERNAL
COMMAND
CKE
ADDRESS
CLK
DQ
CLOCK
CKE
CLK
DQ
READ
BANK a,
COL n
T0
NOP
T0
NOP
T1
WRITE
BANK a,
COL n
D
T1
IN
n
NOP
T2
D
OUT
n
T2
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH; the
internal clock and related operation will resume on the
subsequent positive clock edge.
T3
D
Integrated Silicon Solution, Inc. — www.issi.com
T3
OUT
n+1
NOP
T4
D
NOP
IN
T4
n+1
NOP
D
T5
OUT
D
DON'T CARE
n+2
NOP
IN
T5
n+2
DON'T CARE
NOP
D
T6
OUT
n+3
03/03/09
Rev. F