IS42S32400E-7BL ISSI, Integrated Silicon Solution Inc, IS42S32400E-7BL Datasheet - Page 5

• Manufacturer Part Number: IS42S32400E-7BL
• Description: IC SDRAM 128MBIT 143MHZ 90FBGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S32400E-7BL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1065; IS42S32400E-7BL

IS42S32400E
PIN FUNCTIONS
DQM0-DQM3
DQ0-DQ31
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 00C
08/01/08
BA0, BA1
Symbol
A0-A11
V
V
CAS
CKE
CLK
RAS
WE
V
V
CS
ddq
ssq
dd
ss
Input/Output Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Type
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (column address
A0-A7), with A10 defining auto precharge) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
DQM0 - DQM3 control the four bytes of the I/O buffers (DQ0-DQ31). In read
mode, DQMn control the output buffer. When DQMn is LOW, the corresponding buf-
fer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH imped-
ance state whenDQMn is HIGH. This function corresponds to OE in conventional
DRAMs. In write mode, DQMn control the input buffer. When DQMn is LOW, the
corresponding buffer byte is enabled, and data can be written to the device. When
DQMn is HIGH, input data is masked and cannot be written to the device.
Data on the Data Bus is latched on these pins during Write commands, and buffered after
Read commands.
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
V
V
V
V
ddq
dd
ssq
ss
is the device internal ground.
is the device internal power supply.
is the output buffer ground.
is the output buffer power supply.
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