IS61LF25636A-7.5TQLI-TR ISSI, Integrated Silicon Solution Inc, IS61LF25636A-7.5TQLI-TR Datasheet
IS61LF25636A-7.5TQLI-TR
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IS61LF25636A-7.5TQLI-TR Summary of contents
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... IS61LF25636A IS61VF25636A IS64LF25636A IS61LF51218A IS61VF51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expan- sion and address pipelining • ...
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... ADV ADSC ADSP 18/ BWE BW(a-d) x18: a,b x36: a-d CE CE2 CE2 POWER ZZ DOWN OE 2 MODE A0 CLK BINARY COUNTER A1 CLR MEMORY ARRAY 16/17 18/ ADDRESS REGISTER CE CLK 36 DQ(a-d) BYTE WRITE REGISTERS CLK 2/4/8 INPUT D Q REGISTERS ENABLE REGISTER CLK CE CLK 256Kx36; 512Kx18; 36, ...
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BOTTOM VIEW Integrated Silicon Solution, Inc. Rev. H 07/22/2010 119-PIN BGA 119-Ball, 14x22 mm BGA BOTTOM VIEW 3 ...
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BGA PACKAGE PIN CONFIGURATION DDQ B NC CE2 DQc DQPc E DQc DQc F V DQc DDQ G DQc DQc H DQc DQc DDQ DD K ...
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BGA PACKAGE PIN CONFIGURATION 512k 18 (TOP VIEW DDQ B NC CE2 DQb DQb DDQ G NC DQb H DQb NC J ...
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PBGA PACKAGE PIN CONFIGURATION 256k 36 (TOP VIEW CE2 C DQPc NC V ddq D DQc DQc V ddq E DQc DQc V ddq F DQc DQc ...
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PBGA PACKAGE PIN CONFIGURATION 512k 18 (TOP VIEW CE2 ddq D NC DQb V ddq E NC DQb V ddq F NC DQb ...
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PIN CONFIGURATION 100 DQPc 1 2 DQc 3 DQc 4 VDDQ 5 VSS 6 DQc 7 DQc 8 DQc 9 ...
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PIN CONFIGURATION 100 VDDQ 5 VSS DQb DQb ...
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TRUTH TABLE (1-8) OPERATION ADDRESS CE Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Snooze Mode, Power-Down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Begin Burst External Read Cycle, Begin Burst External Read Cycle, Continue Burst Next Read Cycle, Continue Burst Next Read Cycle, Continue Burst Next Read Cycle, Continue Burst Next Write Cycle, Continue Burst Next Write Cycle, Continue Burst ...
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INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address A1 A0 A1 A0 LINEAR BURST ADDRESS TABLE (MODE = VSS) A1', A0' = 1,1 ABSOLUTE MAxIMUM RATINGS Symbol Parameter T Storage Temperature sTg P Power Dissipation d ...
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OPERATING RANGE (IS61LFxxxxx) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C OPERATING RANGE (IS64LFxxxxx) Range Ambient Temperature Automotive -40°C to +125°C OPERATING RANGE (IS61VFxxxxx) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage Oh V Output LOW Voltage Ol V ...
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CAPACITANCE (1,2) Symbol Parameter c Input Capacitance IN c Input/Output Capacitance OuT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load AC TEST LOADS Z = 50Ω O OUTPUT Figure 1 Integrated ...
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Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O OUTPUT Figure 3 14 Unit 0V to 2.5V 1.5 ns 1.25V OUTPUT 50Ω 1.25V 1,667 Ω +2. Including 1,538 Ω jig and scope Figure 4 Integrated Silicon ...
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READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter fmax Clock Frequency t Cycle Time kc t Clock High Time kh t Clock Low Time kl t Clock Access Time kq t Clock High to Output Invalid (2) kqx t Clock High to Output Low-Z (2,3) kqlZ t Clock High to Output High-Z (2,3) ...
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READ/WRITE CYCLE TIMING CLK ADSP t SS ADSC ADV Address RD1 BWE BWd-BWa t t CES CEH CES CEH CE2 t t CES ...
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WRITE CYCLE TIMING CLK ADSP ADSC ADV must be inactive for ADSP Write ADV Address WR1 BWE t WS BWd-BWa WR1 t t CES CEH CE ...
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SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SNOOZE MODE active to input ignored Pds t ZZ inactive to input sampled Pus t ZZ active to SNOOZE current ZZI t ZZ inactive to exit SNOOZE current rZZI SNOOZE MODE TIMING CLK t PDS ZZ setup cycle ZZ t ...
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IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The IS61LF/VF25636A and IS61LF/VF51218A have a serial boundary scan Test Access Port (TAP) in the PBGA package only. This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. DISABLING THE JTAG FEATURE The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (Vss) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to V ...
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TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register. PERFORMING A TAP RESET A Reset is performed by forcing TMS HIGH (V rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes high-Z state. TAP REGISTERS Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the in- struction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram) At power-up, the instruction register is loaded with the IDCODE instruction also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two ...
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TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buf- fers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/ PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instruc- tions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP control- ler must be moved into the Update-IR state. ExTEST EXTEST is a mandatory 1149.1 instruction which executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The T AP controller recognizes an all-0 instruction. W hen an EXTEST instruction is loaded into the instruction register, the SRAM responds SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instruc- ...
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INSTRUCTION CODES Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register be- tween the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. 010 SAMPLE-Z Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. 011 RESERVED Do Not Use: This instruction is reserved for future use. 100 SAMPLE/PRELOAD Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 RESERVED Do Not Use: This instruction is reserved for future use. 110 RESERVED Do Not Use: This instruction is reserved for future use. 111 BYPASS Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. TAP CONTROLLER STATE DIAGRAM Test Logic Reset ...
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TAP Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage Oh1 V Output HIGH Voltage Oh2 V Output LOW Voltage Ol1 V Output LOW Voltage Ol2 V Input HIGH Voltage Ih V Input LOW Voltage Il I Input Load Current x Notes: 1. All Voltage referenced to Ground. 2. Overshoot: V (AC) ≤ V +1.5V for t Ih ...
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TAP AC TEST CONDITIONS Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage TAP TIMING 1 t THTH TCK TMS TDI TDO 24 TAP Output Load Equivalent 1ns 1.25V/1.5V 1.25V/1.5V 1.25V/1.5V 1.25V/1. TLTH t THTL t t MVTH THMX t t DVTH ...
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Signal Bump B it # Name ID Bit # Name ...
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Signal Bump B it # Name ID Bit # 1 MODE 11P ...
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Signal Bump B it # Name ID Bit # 1 MODE 11P ...
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... IS61LF25636A-6.5TQ IS61LF25636A-6.5B2 IS61LF25636A-6.5B3 IS61LF25636A-7.5TQ IS61LF25636A-7.5B2 IS61LF25636A-7.5B3 IS61LF51218A-6.5TQ IS61LF51218A-6.5TQL IS61LF51218A-6.5B2 IS61LF51218A-6.5B3 IS61LF51218A-7.5TQ IS61LF51218A-7.5B2 IS61LF51218A-7.5B3 Order Part Number IS61LF25636A-6.5TQI IS61LF25636A-6.5B2I IS61LF25636A-6.5B3I IS61LF25636A-7.5TQI IS61LF25636A-7.5TQLI IS61LF25636A-7.5B2I IS61LF25636A-7.5B3I IS61LF51218A-6.5TQI IS61LF51218A-6.5B2I IS61LF51218A-6.5B3I IS61LF51218A-7.5TQI IS61LF51218A-7.5TQLI IS61LF51218A-7.5B2I IS61LF51218A-7.5B3I Order Part Number IS64LF25636A-7.5TQLA3 IS64LF25636A-7.5B3LA3 IS64LF51218A-7.5TQLA3 Package (1) 100 TQFP, 3CE ...
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ORDERING INFORMATION (V Commercial Range: 0°C to +70°C Configuration Access Time 256Kx36 6.5 256Kx36 7.5 512Kx18 6.5 512Kx18 7.5 Industrial Range: -40°C to +85°C Configuration Access Time 256Kx36 6.5 ...
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Integrated Silicon Solution, Inc. Rev. H 07/22/2010 ...
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Integrated Silicon Solution, Inc. Rev. H 07/22/2010 31 ...
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Integrated Silicon Solution, Inc. Rev. H 07/22/2010 ...