IS42S32800B-6BI ISSI, Integrated Silicon Solution Inc, IS42S32800B-6BI Datasheet - Page 14
![no-image](/images/manufacturer_photos/0/3/347/issi__integrated_silicon_solution_inc_sml.jpg)
IS42S32800B-6BI
Manufacturer Part Number
IS42S32800B-6BI
Description
IC SDRAM 256MBIT 166MHZ 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S32800B-7BL.pdf
(62 pages)
Specifications of IS42S32800B-6BI
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (8Mx32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-BGA
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
BGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32800B-6BI
Manufacturer:
ISSI
Quantity:
19
Company:
Part Number:
IS42S32800B-6BI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Company:
Part Number:
IS42S32800B-6BI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS42S32800B
14
· Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank
WRITE with Auto Precharge
· Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n
n when registered. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the WRITE
to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE
to bank m.
when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after
t WR is met, where t WR begins when the READ to bank m is registered. The last valid WRITE to bank n will
be data-in registered one clock prior to the READ to bank m.
Internal
States
Internal
States
NOTE: 1. DQM is LOW.
NOTE: 1. DQM is LOW.
WRITE With Auto Precharge Interrupted by a WRITE
WRITE With Auto Precharge Interrupted by a READ
COMMAND
ADDRESS
BANK m
COMMAND
BANK n
ADDRESS
BANK m
BANK n
CLK
DQ
Page Active
NOP
T0
Page Active
T0
NOP
WRITE - AP
BANK n,
Page Active
BANK n
COL a
T1
D
a
WRITE - AP
IN
BANK n,
WRITE with Burst of 4
Page Active
BANK n
COL a
T1
D
a
IN
WRITE with Burst of 4
a + 1
T2
D
NOP
IN
a + 1
T2
D
NOP
IN
a + 2
T3
D
IN
BANK m,
READ - AP
T3
COL d
BANK m
Interrupt Burst, Write-Back
t
CAS Latency = 3 (BANK m)
WR - BANK n
READ with Burst of 4
BANK m,
WRITE - AP
COL d
BANK m
T4
D
Interrupt Burst, Write-Back
d
t
IN
WR - BANK n
T4
WRITE with Burst of 4
NOP
T5
d + 1
NOP
D
T5
IN
NOP
Precharge
t
RP - BANK n
T6
d + 2
NOP
Precharge
D
t RP - BANK n
IN
T6
D
NOP
OUT
d
DON’T CARE
Integrated Silicon Solution, Inc.
DON’T CARE
T7
d + 3
NOP
D
t WR - BANK m
IN
Write-Back
T7
D
d + 1
NOP
t RP - BANK m
OUT
I
®
07/21/09
Rev. F