IS61WV102416BLL-10TLI-TR ISSI, Integrated Silicon Solution Inc, IS61WV102416BLL-10TLI-TR Datasheet - Page 13
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IS61WV102416BLL-10TLI-TR
Manufacturer Part Number
IS61WV102416BLL-10TLI-TR
Description
IC SRAM 16MBIT 10NS 48TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS61WV102416BLL-10TLI.pdf
(20 pages)
Specifications of IS61WV102416BLL-10TLI-TR
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
16M (1M x 16)
Speed
10ns
Interface
Parallel
Voltage - Supply
2.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IS61WV102416ALL
IS61WV102416BLL
IS64WV102416BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. E
06/05/09
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
levels of 1.25V, input pulse levels of 0.4V to V
100% tested.
must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The
Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that
terminates the write.
WC
AW
HA
SD
HD
SCE
SA
PWB
PWE
PWE
HZWE
LZWE
1
2
(3)
(3)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
DD
-0.3V and output loading specified in Figure 1a.
Min.
20
12
12
12
12
17
—
1-800-379-4774
0
0
9
0
3
-20 ns
(1,2)
Max.
—
—
—
—
—
—
—
—
—
—
—
9
(Over Operating Range)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13