IS42S32160C-75BL ISSI, Integrated Silicon Solution Inc, IS42S32160C-75BL Datasheet - Page 22

• Manufacturer Part Number: IS42S32160C-75BL
• Description: IC SDRAM 512MBIT 133MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32160C-75BL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (16M x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-BGA
• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: WBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 260mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S32160C
22
7.
8.
9.
10. Assumed input rise and fall time t
11. Power up Sequence
LVTTL Interface
Reference Level of Output Signals
Output Load
Input Signal Levels
Transition Time (Rise and Fall)of Input Signals
Reference Level of Input Signals
Transition times are measured between VIH and VIL.Transition(rise and fall) of input signals are in a fixed slope
(1 ns).
t
If clock rising time is longer than 1 ns, (t
If t
should be added to the parameter.
Power up must be performed in the following sequence.
(i) Power must be applied to V
and both CKE =”H”and DQM =”H.”The CLK signals must be started at the same time
(ii) After power-up,a pause of 200µ seconds minimum is required.Then,it is recommended that DQM is
held “HIGH”(V
(iii) All banks must be precharged.
(iv) Mode Register Set command must be asserted to initialize the Mode register.
(v) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.
HZ
R
defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
Output
or t
LVTTL A.C. Test Load
F
is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns
DD
Z0=
levels)to ensure DQ output is in high impedence.
50 Ω
DD
T
and V
30pF
50Ω
1.4V
(t
R
&t
DDQ
R
F
/2 -0.5)ns should be added to the parameter.
)= 1 ns
(simultaneously) when all input signals are held “NOP”state
1.4V /1.4V
Reference to the Under Output Load
2.4V /0.4V
1ns
1.4V
Integrated Silicon Solution, Inc.
Rev. B
01/22/09