IS42S16320B-7TLI ISSI, Integrated Silicon Solution Inc, IS42S16320B-7TLI Datasheet - Page 47
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IS42S16320B-7TLI
Manufacturer Part Number
IS42S16320B-7TLI
Description
IC SDRAM 512MBIT 143MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S16320B-7TL-TR.pdf
(62 pages)
Specifications of IS42S16320B-7TLI
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (32Mx16)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
54-TSOP II
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Data Bus Width
16 bit
Maximum Clock Frequency
143 MHz
Access Time
6.5 ns, 5.4 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
130 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S16320B-7TLI
Manufacturer:
ISSI
Quantity:
5 530
Company:
Part Number:
IS42S16320B-7TLI
Manufacturer:
ISSI
Quantity:
1 000
IS42S86400B, IS42/45S16320B
PRECHARGE
The PRECHARGE command (see figure) is used to deac-
tivate the open row in a particular bank or the open row in
all banks. T he bank(s) will be available for a subsequent row
access some specified time (t
command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. When all banks are to be precharged, inputs BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers, excluding CKE, for maximum power savings while
in standby. The device may not remain in the power-down
state longer than the refresh period (64ms) since no refresh
operations are performed in this mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting t
POWER-DOWN
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
04/08/2011
cks
COMMAND
). See figure "Power-Down".
CKE
CLK
All banks idle
Enter power-down mode
rp
) after the PRECHARGE
t
NOP
CKS
Input buffers gated off
less than 64ms
PRECHARGE Command
Exit power-down mode
A0-A9, A11, A12
BA0, BA1
CKE
RAS
CAS
CLK
A10
WE
≥ t
CS
CKS
NOP
HIGH
DON'T CARE
ACTIVE
BANK ADDRESS
BANK SELECT
ALL BANKS
t
t
t
RCD
RAS
RC
47