IS61LF102418A-7.5TQ-TR ISSI, Integrated Silicon Solution Inc, IS61LF102418A-7.5TQ-TR Datasheet
IS61LF102418A-7.5TQ-TR
Specifications of IS61LF102418A-7.5TQ-TR
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IS61LF102418A-7.5TQ-TR Summary of contents
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... IS61LF25672A IS61VF25672A IS61LF51236A IS61VF51236A IS61LF102418A IS61VF102418A 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • ...
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... IS61LF25672A IS61LF51236A IS61VF25672A IS61VF51236A IS61VF102418A BLOCK DIAGRAM CLK ADV ADSC ADSP 19/ BWE BW(a-h) x18: a,b x36: a-d x72: a-h CE CE2 CE2 POWER ZZ DOWN OE 2 IS61LF102418A MODE A0 CLK BINARY COUNTER A1 CLR MEMORY ARRAY 17/18 19/ ADDRESS REGISTER CE CLK 36, DQ(a-d) BYTE WRITE REGISTERS CLK ...
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... IS61LF25672A IS61LF51236A IS61VF25672A IS61VF51236A IS61VF102418A 165-PIN BGA 165-Ball, 13x15 mm BGA BOTTOM VIEW 209-BALL BGA 209-Ball BGA 1 mm Ball Pitch Ball Array BOTTOM VIEW Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A 119-PIN BGA 119-Ball, 14x22 mm BGA BOTTOM VIEW 3 ...
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... Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select BWx (x=a,b,c,d Synchronous Byte Write e,f,g,h) Controls 4 IS61LF102418A ADSP ADSC ADV CE2 BWg BWE NC A BWd ...
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... Synchronous Burst Address Advance. ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE Synchronous Chip Select BWx (x=a-d) Synchronous Byte Write Controls BWE Byte Write Enable Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A 512K 36 (TOP VIEW ADSP ADSC ...
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... A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance. ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Controls BWE Byte Write Enable 6 IS61LF102418A ADSP ADSC Vss ...
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... ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select BWx (x=a,b,c,d) Synchronous Byte Write Controls Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A BWc BWb CE2 BWE BWd BWa GW CLK Vss Vss ...
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... ADV Synchronous Burst Address Advance. ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Controls 8 IS61LF102418A BWb CE2 BWE NC BWa GW NC CLK Vss Vss Vss Vss ...
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... ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQd Synchronous Data Input/Output Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A 80 DQPb 79 DQb 78 DQb 77 VDDQ 76 VSS 75 DQb 74 DQb ...
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... ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQb Synchronous Data Input/Output 10 IS61LF102418A VDDQ 76 VSS DQPa 73 ...
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... ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A ...
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... BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. PARTIAL TRUTH TABLE BWE BWE BWE BWE BWE Function Read H H Read H L Write Byte Write All Bytes H L Write All Bytes IS61LF102418A ADDRESS ADSP ADSP ADSP ADSP ADSP ADSC ADSC ADSC ADSC ADSC None External External External ...
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... This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A or No Connect) DD 2nd Burst Address 3rd Burst Address A1 A0 ...
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... Sleep Mode ZZ> Note: 1. MODE pin has an internal pullup and should be tied 0.2V or ≥ – 0.2V IS61LF102418A V DD 3.3V ± 5% 3.3V/2.5V ± 5% 3.3V ± 5% 3.3V/2.5V ± 2.5V ± 5% 2.5V ± 5% (Over Operating Range) 3.3V Min. = –4.0 mA (3.3V) 2 –1.0 mA (2.5V 8.0 mA (3.3V) — ...
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... Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load AC TEST LOADS Z = 50Ω O OUTPUT Figure 1 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A Conditions Max OUT = 3.3V. DD Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3 ...
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... Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O OUTPUT Figure 3 16 IS61LF102418A Unit 0V to 2.5V 1.5 ns 1.25V OUTPUT 50Ω 1.25V 1,667 Ω +2. Including 1,538 Ω ...
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... Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A (1) (Over Operating Range) 6.5 7.5 Min. Max. Min. Max. ...
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... CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT t KQLZ t KQ High-Z DATA IN Single Read Flow-through 18 IS61LF102418A ADSP is blocked by CE inactive t SH WR1 RD2 WR1 CE2 and CE2 only sampled with ADSP or ADSC t OEHZ t OEQX High KQLZ t ...
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... CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT t DS High-Z DATA IN 1a Single Write Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A ADSP is blocked by CE1 inactive t t AVH AVS WR2 WR2 CE1 Masks ADSP CE2 and CE3 only sampled with ADSP or ADSC ...
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... RZZI SNOOZE MODE TIMING CLK t PDS ZZ setup cycle ZZ t ZZI Isupply I SB2 All Inputs Deselect or Read Only (except ZZ) Outputs (Q) 20 IS61LF102418A Conditions Min. ZZ ≥ Vih — — 2 — recovery cycle t RZZI Deselect or Read Only High-Z Integrated Silicon Solution, Inc. Max. Unit 60 ...
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... TAP CONTROLLER TMS Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A TEST ACCESS PORT (TAP) - TEST CLOCK The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK. ...
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... ISSI JEDEC ID (11:1) Allows unique identification of SRAM vendor. 00011010101 ID Register Presence (0) Indicate the presence register. 22 IS61LF102418A is set LOW (Vss) when the BYPASS instruction is ex- ecuted. Boundary Scan Register The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices ...
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... TAP controller Shift-DR state. It also places all SRAM outputs into a High-Z state. Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not imple- mented, so the TAP controller is not fully 1149.1 compli- ant ...
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... Do Not Use: This instruction is reserved for future use. 111 BYPASS Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. TAP CONTROLLER STATE DIAGRAM Test Logic Reset 1 0 Run Test/Idle 0 24 IS61LF102418A 1 1 Select Capture DR 0 Shift ...
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... Notes: 1. Both t and t refer to the set-up and hold time requirements of latching data from the boundary scan register Test conditions are specified using the load in TAP AC test conditions. t Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A (1,2) Test Conditions I = –2 –100 μ 2 100 μ ...
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... Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage TAP TIMING 1 t THTH TCK TMS TDI TDO 26 IS61LF102418A TAP Output Load Equivalent 1ns 1.25V/1.5V 1.25V/1.5V 1.25V/1.5V 1.25V/1. TLTH t THTL t ...
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... DQa 11J 36 17 DQa 10M 37 18 DQa 10L 38 19 DQa 10K 39 20 DQa 10J 40 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A Signal Bump Signal Name ID Bit # Name DQb 11G 41 NC CE2 DQb 11F 42 BWa DQb 11E 43 BWb DQb 11D 44 BWc ...
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... NC 11L 11K 11J 36 17 DQa 10M 37 18 DQa 10L 38 19 DQa 10K 39 20 DQa 10J 40 28 IS61LF102418A Signal Bump Signal Name ID Bit # Name DQa 11G 41 NC CE2 DQa 11F 42 BWa DQa 11E 43 DQa 11D 44 NC BWb DQa 11C 45 NC 10F ...
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... IS61LF25672A IS61LF51236A IS61VF25672A IS61VF51236A IS61VF102418A 209 BOUNDARY SCAN ORDER (256K X 72) Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A 29 ...
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... Order Part Number IS61LF25672A-6.5B1I IS61LF51236A-6.5TQI IS61LF51236A-6.5TQLI IS61LF51236A-6.5B2I IS61LF51236A-6.5B2LI IS61LF51236A-6.5B3I IS61LF51236A-7.5TQI IS61LF51236A-7.5TQLI IS61LF51236A-7.5B2I IS61LF51236A-7.5B3I IS61LF51236A-7.5B3LI IS61LF102418A-6.5TQI IS61LF102418A-6.5B2I IS61LF102418A-6.5B3I IS61LF102418A-7.5TQI IS61LF102418A-7.5TQLI IS61LF102418A-7.5B2I IS61LF102418A-7.5B3I IS61LF102418A-7.5B3LI Package 209 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 100 TQFP, Lead-free ...
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... Industrial Range: -40°C to +85°C Configuration Access Time 256Kx72 6.5 512Kx36 6.5 512Kx36 7.5 1Mx18 6.5 1Mx18 7.5 Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A = 2. 2.5V) DD DDQ Order Part Number IS61VF25672A-6.5B1 IS61VF51236A-6.5TQ IS61VF51236A-6.5B2 IS61VF51236A-6.5B3 IS61VF51236A-7.5TQ IS61VF51236A-7.5B2 IS61VF51236A-7.5B3 IS61VF102418A-6.5TQ IS61VF102418A-6.5B2 IS61VF102418A-6.5B3 IS61VF102418A-7.5TQ IS61VF102418A-7 ...
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... IS61LF25672A IS61LF51236A IS61VF25672A IS61VF51236A IS61VF102418A 32 IS61LF102418A Integrated Silicon Solution, Inc. Rev. K 07/29/2010 ...
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... IS61LF25672A IS61LF51236A IS61VF25672A IS61VF51236A IS61VF102418A Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A 33 ...
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... IS61LF25672A IS61LF51236A IS61VF25672A IS61VF51236A IS61VF102418A 34 IS61LF102418A Integrated Silicon Solution, Inc. Rev. K 07/29/2010 ...
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... IS61LF25672A IS61LF51236A IS61VF25672A IS61VF51236A IS61VF102418A Integrated Silicon Solution, Inc. Rev. K 07/29/2010 IS61LF102418A 35 ...