IS61NVP51236-200TQLI ISSI, Integrated Silicon Solution Inc, IS61NVP51236-200TQLI Datasheet - Page 22

• Manufacturer Part Number: IS61NVP51236-200TQLI
• Description: IC SRAM 18MBIT 200MHZ 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61NVP51236-200TQLI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Density: 18Mb
• Access Time (max): 3.1ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 475mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61NLP and IS61NVP have a serial boundary scan
Test Access Port (TAP) in the PBGA package only. (Not
available in TQFP package.) This port operates in accor-
dance with IEEE Standard 1149.1-1900, but does not
include all functions required for full 1149.1 compliance.
These functions from the IEEE specification are excluded
because they place added delay in the critical speed path
of the SRAM. The TAP controller operates in a manner that
does not conflict with the performance of other devices
using 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature. To
disable the TAP controller, TCK must be tied LOW (V
prevent clocking of the device. TDI and TMS are internally
pulled up and may be disconnected. They may alternately
be connected to V
be left disconnected. On power-up, the device will start in a
reset state which will not interfere with the device operation.
TAP CONTROLLER BLOCK DIAGRAM
22
TMS
TCK
TDI
Selection Circuitry
DD
TAP CONTROLLER
through a pull-up resistor. TDO should
31 30 29
0
2
x
Bypass Register
Instruction Register
Identification Register
Boundary Scan Register*
. . . . .
1
0
SS
) to
. . .
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any
register. The register between TDI and TDO is chosen by
the instruction loaded into the TAP instruction register.
For information on instruction register loading, see the
TAP Controller State Diagram. TDI is internally pulled up
and can be disconnected if the TAP is unused in an
application. TDI is connected to the Most Significant Bit
(MSB) on any register.
Integrated Silicon Solution, Inc. — www.issi.com
2
2
1
1
0
0
Selection Circuitry
TDO
06/26/08
Rev. L