IS61LF51236A-7.5TQI ISSI, Integrated Silicon Solution Inc, IS61LF51236A-7.5TQI Datasheet - Page 12
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IS61LF51236A-7.5TQI
Manufacturer Part Number
IS61LF51236A-7.5TQI
Description
IC SRAM 18MBIT 7.5NS 100TQFP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS61LF51236A-7.5TQLI-TR.pdf
(35 pages)
Specifications of IS61LF51236A-7.5TQI
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
18M (512K x 36)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS61LF51236A-7.5TQI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Company:
Part Number:
IS61LF51236A-7.5TQI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS61LF25672A
IS61VF25672A
TRUTH TABLE
NOTE:
12
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all
3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and
4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
NEXT CYCLE
Deselected
Read, Begin Burst
Read, Begin Burst
Write, Begin Burst
Read, Begin Burst
Read, Begin Burst
Read, Continue Burst
Read, Continue Burst
Read, Continue Burst
Read, Continue Burst
Write, Continue Burst
Write, Continue Burst
Read, Suspend Burst
Read, Suspend Burst
Read, Suspend Burst
Read, Suspend Burst
Write, Suspend Burst
Write, Suspend Burst
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
BWx, BWE, GW HIGH.
DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s
and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are available
on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
the input data hold time.
enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
(1-8)
(1CE option)
GW
GW
GW
GW
GW
IS61LF51236A
IS61VF51236A IS61VF102418A
H
H
H
H
L
BWE
BWE
BWE
BWE
BWE
H
L
L
L
X
ADDRESS CE
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
BWa
BWa
BWa
BWa
BWa
Next
Next
Next
Next
Next
Next
H
X
X
L
L
IS61LF102418A
BWb
BWb
BWb
BWb
BWb
CE
CE
CE
CE
H
H
H
X
X
H
H
X
H
X
X
H
H
X
H
X
X
L
L
L
L
L
L
ADSP
ADSP
ADSP
ADSP
ADSP
BWc
BWc
BWc
BWc
BWc
H
H
H
H
H
H
H
H
H
H
H
X
X
X
L
X
X
X
X
X
X
L
L
ADSC
ADSC
ADSC
ADSC
ADSC
BWd
BWd
BWd
BWd
BWd
X
H
H
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
BWe
BWe
BWe
BWe
BWe
ADV
ADV
ADV
ADV
ADV
X
H
H
X
X
H
H
H
H
H
H
L
X
X
X
X
X
L
L
L
L
L
L
Integrated Silicon Solution, Inc.
WRITE
WRITE
WRITE
WRITE
WRITE
BWf
BWf
BWf
BWf
BWf
X
H
H
X
L
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
BWg
BWg
BWg
BWg
BWg
OE
OE
OE
OE
OE
X
H
H
X
L
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
L
BWh
BWh
BWh
BWh
BWh
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
H
H
X
L
X
DQ
07/29/2010
Q
D
Q
Q
Q
D
D
Q
Q
D
D
Rev. K