M25P05-AVMN6P NUMONYX, M25P05-AVMN6P Datasheet - Page 28

• Manufacturer Part Number: M25P05-AVMN6P
• Description: IC FLASH 512KBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P05-AVMN6P

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.3V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Base Number: 25
• Frequency: 50MHz
• Ic Generic Number: 25P05
• Memory Configuration: 64K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Instructions
6.8
28/52
Page program (PP)
The page program (PP) instruction allows bytes to be programmed in the memory (changing
bits from 1 to 0). Before it can be accepted, a write enable (WREN) instruction must
previously have been executed. After the write enable (WREN) instruction has been
decoded, the device sets the write enable latch (WEL).
The page program (PP) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, three address bytes and at least one data byte on Serial Data input (D). If
the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see
times).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the page program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose
duration is t
may be read to check the value of the write in progress (WIP) bit. The write in progress
(WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the write enable latch (WEL) bit is
reset.
A page program (PP) instruction applied to a page which is protected by the block protect
(BP1, BP0) bits (see
PP
) is initiated. While the page program cycle is in progress, the status register
Table 3.
and
Table
Figure 14.
2.) is not executed.
Table 14: Instruction
M25P05-A