M25P40-VMP6TG NUMONYX, M25P40-VMP6TG Datasheet - Page 31
![IC FLASH 4MBIT 50MHZ 8VFQFPN](/photos/18/97/189768/3778330_sml.jpg)
M25P40-VMP6TG
Manufacturer Part Number
M25P40-VMP6TG
Description
IC FLASH 4MBIT 50MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P40-VMP6G.pdf
(61 pages)
Specifications of M25P40-VMP6TG
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Memory Configuration
512K X 8
Ic Interface Type
Serial, SPI
Clock Frequency
50MHz
Supply Voltage Range
2.3V To 3.6V
Memory Case Style
VDFPN
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P40-VMP6TG
Manufacturer:
st
Quantity:
11 116
Part Number:
M25P40-VMP6TG
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P40-VMP6TG-X
Manufacturer:
STM
Quantity:
12 000
Part Number:
M25P40-VMP6TG-X
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M25P40-VMP6TG/TE
Manufacturer:
ST
Quantity:
2 000
6.10
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is t
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits
are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 16. Bulk Erase (BE) instruction sequence
S
C
D
0
Figure
1
2
Instruction
16.
3
4
5
6
7
AI03752D
BE
) is initiated. While the
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