M25PE16-VMW6TG NUMONYX, M25PE16-VMW6TG Datasheet - Page 57
![IC FLASH 16MBIT 75MHZ 8SOIC](/photos/7/28/72835/m25pe16-vmw6tg_sml.jpg)
M25PE16-VMW6TG
Manufacturer Part Number
M25PE16-VMW6TG
Description
IC FLASH 16MBIT 75MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M45PE16-VMP6TG.pdf
(58 pages)
Specifications of M25PE16-VMW6TG
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
16M (2M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Package
8SOIC W
Cell Type
NOR
Density
16 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
64KByte x 32
Timing Type
Synchronous
Interface Type
Serial-SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
M25PE16-VMW6TGTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25PE16-VMW6TG
Manufacturer:
MAXIM
Quantity:
14 500
Company:
Part Number:
M25PE16-VMW6TG
Manufacturer:
Numonyx
Quantity:
15 000
Part Number:
M25PE16-VMW6TG
Manufacturer:
ST
Quantity:
20 000
M25PE16
14
Revision history
Table 25.
07-Aug-2006
20-Nov-2006
16-Feb-2006
25-Mar-2008
13-Oct-2006
12-Apr-2007
01-Apr-2008
Date
Document revision history
Revision
0.1
1
2
3
4
5
6
Applied Numonyx branding.
Initial release.
Figure 3: Bus master and memory devices on the SPI bus
and
Section 4.8.1: Protocol-related protections
Address range for subsector 15 of sector 0 modified in
Memory
RESET signal behavior clarified in
(WRSR),
(PP),
(SSE),
Section 8: Reset
Low pulse. Table Reset while a Read, Program or Erase cycle is in
progres replaced by
Table 19
updated. Small text changes.
HPM2 specified in
Table 12: Device status after a Reset Low pulse
V
f
(50 MHz
TSL/W signal renamed as W, Top Sector Lock functionality removed,
HPM2 removed.
Paragraph added in
Absolute maximum
Table 18: AC characteristics (50 MHz operation)
Write protect setup and hold
updated (see
Document status promoted from preliminary data to datasheet.
supply voltage
memory devices on the SPI bus
replaced by an explanatory paragraph.
Behavior of WIP bit and lock registers specified at power-up in
Section 7: Power-up and
VFQFPN8 package specifications updated (see
Table
Removed ‘low voltage’ from the title.
Updated the value for the maximum clock frequency (from 50 to
75 MHz) through the document.
Added:
ECOPACK® text in
Modified:
Minor text changes.
R
IO
, t
W
max. modified in
Note 2
, t
Section 6.12: Page erase
22).
PW
Section 6.15: Bulk erase
Table 19: AC characteristics (75 MHz operation)
organization.
split into two tables (see also
operation).
Section 6.9: Page write
Section 3: SPI modes
, t
added.
PP
Table 23
and t
and
added to describe the device status after a RESET
HPM1 and HPM2
VSS ground
Section 12: Package
ratings. t
SSE
Section 3: SPI
Table 21: Timings after a Reset Low pulse
Table 13: Absolute maximum
and
modified in
power-down.
Figure
THSL
timing. SO8W package specifications
Changes
(PE),
added.
and
(BE).
updated, Note 2 removed and
(PW),
and t
30).
Section 6.5: Write status register
modes. T
Table 18: AC characteristics
Table 17: DC
paragraph. Small text changes.
Section 6.14: Subsector erase
Table
SHTL
Figure 3: Bus master and
Section 6.10: Page program
mechanical.
clarified.
timings removed from
LEAD
20). t
modified.
Figure 29
and
added to
Revision history
BE
characteristics.
ratings.
typical value
Figure 26:
Table 4:
and
and
updated
Table 13:
VCC
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