M25P32-VMF6P NUMONYX, M25P32-VMF6P Datasheet - Page 30
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M25P32-VMF6P
Manufacturer Part Number
M25P32-VMF6P
Description
IC FLASH 32MBIT 75MHZ 16SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P32-VME6G.pdf
(54 pages)
Specifications of M25P32-VMF6P
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
32M (4M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC
Package
16SO W
Cell Type
NOR
Density
32 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
64KByte x 64
Timing Type
Synchronous
Interface Type
Serial-SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-3597
497-3597
497-3597
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P32-VMF6P,M25P32-VMF6TP
Quantity:
5 000
Company:
Part Number:
M25P32-VMF6PB
Manufacturer:
INTEL
Quantity:
10 000
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For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes.
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is t
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see
Figure 15. Page Program (PP) instruction sequence
1. Address bits A23 to A22 are Don’t Care.
S
C
D
S
C
D
MSB
7
40
PP
6
41
) is initiated. While the Page Program cycle is in progress, the Status Register
0
5
42
Data Byte 2
1
4
43 44 45 46 47 48 49 50
2
Instruction
3
3
2
4
Table 2
1
5
0
6
MSB
7
and
7
MSB
6
23
8
Table
5
22 21
Data Byte 3
9 10
24-Bit Address
4
51
3) is not executed.
3
52 53 54 55
2
3
28 29 30 31 32 33 34 35
1
2
0
1
0
MSB
7
MSB
7
6
6
Data Byte 256
5
5
Data Byte 1
4
4
3
3
36 37 38
2
2
1
1
0
0
39
AI04082B