N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet
N25Q128A13BF840F
Specifications of N25Q128A13BF840F
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N25Q128A13BF840F Summary of contents
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... XiP Enabled, Serial Flash Memory with 108 MHz SPI Bus Interface Features SPI-compatible serial bus interface 108 MHz (maximum) clock frequency 2 3.6 V single supply voltage Supports legacy SPI protocol and new Quad I/O or Dual I/O SPI protocol Quad/Dual I/O instructions resulting in an ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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N25Q128 - 3 V 5.2 Dual SPI (DIO-SPI) Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.1 SPI Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . . . 46 8 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1 Extended SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 9.1.9 9.1.10 9 ...
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N25Q128 - 3 V 9.1.14 9.1.15 9.1.16 9.1.17 9.1.18 9.1.19 9.1.20 9.1.21 9.1.22 9.1.23 9.1.24 9.1.25 9.1.26 9.1.27 9.1.28 9.1.29 9.1.30 9.1.31 9.1.32 9.1.33 9.1.34 9.1.35 9.2 DIO-SPI Instructions . . . . . . . . . . . ...
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... Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 104 Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 104 Reset Enable and Reset Memory, Dual I 105 Multiple I/O Read Identification (MIORDID 108 Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . 109 Quad Command Fast Read (QCFR 110 Read OTP (ROTP) ...
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... Enter XIP mode by setting the Non Volatile Configuration Register . . . . 133 10.2 Enter XIP mode by setting the Volatile Configuration Register . . . . . . . 134 10.3 XIP mode hold and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10.4 XIP Memory reset after a controller reset . . . . . . . . . . . . . . . . . . . . . . . . 136 11 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 11.1 Rescue sequence in case of power loss during WRNVCR . . . . . . . . . . 138 12 Initial delivery state ...
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... Software protection truth table (Sectors 0 to 255, 64 Kbyte granularity Table 10. Protected area sizes, Upper (TB bit = Table 11. Protected area sizes, Lower (TB bit = Table 12. Memory Map Sectors 255:128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 13. Memory Map Sectors 127: Table 14. Memory Map Sectors 63 Table 15. Instruction set: extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 16 ...
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... Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. VDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. BGA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Extended SPI protocol example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 8. Non Volatile and Volatile configuration Register Scheme . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 9. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 10 ...
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... Read Volatile Enhanced Configuration Register instruction sequence DIO-SPI . . . . . . . 104 Figure 70. Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI . . . . . . . 105 Figure 71. Reset Enable and Reset Memory Instruction Sequence, Dual I 106 Figure 72. Multiple I/O Read Identification instruction and data-out sequence QIO-SPI . . . . . . . . . . 109 Figure 73. ...
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... N25Q128 - 3 V Figure 101. Reset Enable and Reset Memory Instruction Sequence, Quad I 130 Figure 102. N25Q128 Read functionality Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 103. XIP mode directly after power 134 Figure 104. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example 135 Figure 105 ...
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... Description 1 Description The N25Q128 is a 128 Mbit (16Mb x 8) serial Flash memory, with advanced write protection mechanisms accessed by a high speed SPI-compatible bus and features the possibility to work in XIP (“eXecution in Place”) mode. The N25Q128 supports innovative, high-performance quad/dual I/O instructions, these new instructions allow to double or quadruple the transfer bandwidth for read and program operations ...
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... Many different N25Q128 configurations are available, please refer to the ordering scheme page for the possibilities. Additional features are available as security options (The Security features are described in a dedicated Application Note). Please contact your nearest Numonyx Sales office for more information. Figure 1. Logic diagram Note: Reset functionality is available in devices with a dedicated part number ...
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Description Figure 2. VDFPN8 connections 1. Reset functionality available in devices with a dedicated part number. See information. Figure 3. SO16 connections don’t use. 2. See Package mechanical 3. Reset functionality available in devices with a dedicated ...
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N25Q128 - Signal descriptions 2.1 Serial data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). When used as ...
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... When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output is high impedance. Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost ...
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... W or VPP are selected by the voltage range applied to the pin. If the W/VPP input is kept in a low voltage range ( VCC) the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP[0:3] bits of the Status Register. (See Table 2 ...
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... The difference between the two modes, as shown in bus master is in standby mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 5. Bus master and memory devices on the SPI bus SPI interface with (CPOL, CPHA (1, 1) SPI Bus Master ...
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N25Q128 - parasitic capacitance of the bus line) is shorter than the time during which the bus p master leaves the SPI bus in high impedance. Example pF, that is R*C p master ...
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... SPI Protocols 4 SPI Protocols The N25Q128 memory can work with 3 different Serial protocols: Extended SPI protocol. Dual I/O SPI (DIO-SPI) protocol. Quad I/O SPI (QIO-SPI) protocol. 4.1 Selecting and Enabling a Protocol It is possible to choose among and enable or disable any of the three protocols by the user volatile or non-volatile configuration bit settings (VECR or NVCR bits) ...
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N25Q128 - 3 V Also when in DIO-SPI mode, the device can be driven by a micro controller in either of the two following modes: CPOL= 0, CPHA= 0 CPOL= 1, CPHA= 1 Please refer to the SPI modes for ...
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SPI Protocols This mode can be set using two ways Volatile: by setting bit 7 of the VECR to 0, the device enters QIO-SPI protocol immediately after the Write Enhanced Volatile Configuration Register sequence completes. The device returns to the ...
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... Read Operations To read the memory content in Extended SPI protocol different instructions are available: READ, Fast Read, Dual Output Fast Read, Dual Input Output Fast Read, Quad Output Fast Read and Quad Input Output Fast read, allowing the application to choose an instruction to send addresses and receive data by one, two or four data lines ...
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... Write, Program or Erase cycle is complete. The information on the memory being in progress for a Program, Erase, or Write instruction can be checked either on the Write In Progress (WIP) bit of the Status Register or in the Program/Erase Controller bit of the Flag Status Register. ...
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N25Q128 - 3 V 5.1.9 Active power and standby power modes When Chip Select (S) is Low, the device is selected, and in the active power mode. When Chip Select (S) is High, the device is deselected, but could remain ...
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... Dual Command Fast reading Reading the memory data multiplexing the instruction, the addresses and the output data on 2 data lines can be achieved in DIO-SPI protocol by mean of the Dual Command Fast Read instruction, that has 3 instruction codes (BBh, 3Bh and 0Bh) to help the application code porting from Extended SPI protocol to DIO-SPI protocol ...
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... Subsector Erase, Sector Erase and Bulk Erase Similar to the Extended SPI protocol, in the DIO-SPI protocol to erase the memory bytes to all 1s (FFh) the Subsector Erase (SSE), the Sector Erase (SE) and the Bulk Erase (BE) instructions are available. These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE) ...
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... Program instruction using (02h, 12h and 32h). The instruction, address and input data are transmitted across 4 data lines The Dual and Single I/O Program instructions are not available in QIO-SPI protocol Programming the memory by multiplexing the instruction, the addresses and the output data on 4 wires can be achieved in QIO-SPI protocol by mean of the Quad Command Page 28/157 Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... Subsector Erase, Sector Erase and Bulk Erase Similar to the Extended SPI protocol, Subsector Erase (SSE), the Sector Erase (SE) and the Bulk Erase (BE) instructions are used to erase the memory in the QIO-SPI protocol. These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE). ...
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... The HOLD (Hold) feature (or Reset feature, for parts having the reset functionality instead of hold) is disabled in QIO-SPI protocol when the device is selected: the Hold (or Reset)/ DQ3 pin always behaves as an I/O pin (DQ3 function) when the device is deselected. For parts with reset functionality still possible to reset the memory when it is deselected (C signal high). 5.3.9 ...
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... Please note that on the next power on the memory will start again in the working protocol set by the Non Volatile Register parameters. ...
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... Each register can be read and modified by means of dedicated instructions in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI). Reading time for all registers is comparable; writing time instead is very different: NVCR bits are set as Flash Cell memory content requiring a longer time to perform internal writing cycles. See Table 36.: AC ...
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... Status register write protect 6.1.1 WIP bit The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write Status Register, (WRSR), Write Non-Volatile Configuration Register (WRNVCR), Write Volatile Configuration Register (WRVCR), Write Volatile Enhanced Configuration Register (WRVECR), Program or Erase cycle instruction is accepted. ...
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... Non Volatile Configuration Register The Non Volatile Configuration Register (NVCR) bits affects the default memory configuration after power-on. It can be used to make the memory start in the configuration to fit the application requirements. The device is delivered with Non Volatile Configuration Register (NVCR) bits all erased to 1 (FFFFh) ...
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N25Q128 - 3 V Table 3. Non-Volatile Configuration Register Bit Parameter Dummy clock NVCR<15:12> cycles XIP enabling NVCR<11:9> at POR Output Driver NVCR<8:6> Strength Value Description 0000 As '1111' 0001 1 0010 2 0011 3 0100 4 0101 5 0110 ...
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... The default values of these bits allow the memory to be safely used with fast read instructions at the maximum frequency (108 MHz). Please note that if the dummy clock number is not sufficient for the operating frequency, the memory reads wrong data ...
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... SPI protocol directly after the power on sequence. The products are delivered with this bit set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in DIO-SPI protocol right after the next power on. ...
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... Volatile Configuration Register The Volatile Configuration Register (VCR) affects the memory configuration after execution of Write Volatile Configuration Register (WRVCR) instruction: it overwrites the memory configuration set at POR by the Non Volatile Configuration Register (NVCR) to define the dummy clock cycles number and makes the device ready to enter in the required XIP mode. ...
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... The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set enable the memory working on XIP mode. For devices with a feature set digit equal the part number (Basic XiP), this bit is always Don't Care, and it is possible to operate the memory in XIP mode without setting ...
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... VECR<2:0> Strength 6.4.1 Quad Input Command VECR<7> The Quad Input Command configuration bit can be used to make the memory start working in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register 40/157 WARNING: in case of both QIO-SPI and DIO-SPI enabled, the memory works in QIO-SPI ...
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... N25Q128 - 3 V (WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set back to 1 the memory start working again in Extended SPI protocol, unless the bit 6 is set to 0 (in this case the memory start working in DIO-SPI mode) ...
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... Erase Suspend bit and Program Suspend bit) are a “Status Indicator bit”, they are set and reset automatically by the memory. Four bits (Erase error bit, Program error bit, VPP error bit and Protection error bit) are “Error Indicators bits”, they are set by the memory when some program or erase operation fails or the user tries to perform a forbidden operation ...
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N25Q128 - 3 V 6.5.1 P/E Controller Status bit The bit 7 of the Flag Status register represents the Program/Erase Controller Status bit, It indicates whether there is a Program/Erase internal cycle active. When P/E Controller Status bit is Low ...
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Volatile and Non Volatile Registers When the Program Status bit is High (FSR<4>=1) after a Program failure that means that the P/E Controller has applied the maximum pulses number to the bytes and it still failed to verify that the ...
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N25Q128 - 3 V The sector is protected by Software Protection Mode 2 (SPM2) Block Protect Bits (standard SPI Status Register), An attempt to program OTP when locked, A Write Status Register command (WRSR) on STD SPI Status Register when ...
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... Specific hardware and software protection There are two software protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. The SPM2 can be locked by hardware with the help of the W input pin. 46/157 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Write Lock and Lock Down bits can be changed. The definition of the Lock Register bits is given in SPM2 The second software protected mode (SPM2) uses the Block Protect bits (BP3, BP2, BP1, BP0) and the Top/Bottom bit (TB bit) to allow part of the memory to be configured as read- only. See Section 16: Ordering Table 9. ...
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... Sectors 0 to 191 Lower half (sectors 0 to 127) None None None None None None None Memory Content Unprotected Area All sectors (sectors 0 to 255) Sectors 1 to 255 Sectors 2 to 255 Sectors 4 to 255 Sectors 8 to 255 Sectors 16 to 255 Sectors 32 to 255 ...
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... TB bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area 1 All sectors 0 All sectors 1 All sectors Micron Technology, Inc., reserves the right to change products or specifications without notice. Protection modes Memory Content Unprotected Area None None None ©2010 Micron Technology, Inc. All rights reserved. 49/157 ...
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... Kbytes each) 4,096 subsectors (4 Kbytes each) 65,536 pages (256 bytes each) 64 OTP bytes located outside the main memory array Each page can be individually programmed: bits are programmed from The device is Subsector eraseble, Sector eraseble, or Bulk Erasable, but not Page Erasable: bits are erased from ...
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... N25Q128 - 3 V Table 12. Memory Map Sectors 255:128 Sector 4095 4094 4093 255 4092:4083 4082 4081 4080 4079 4078 4077 254 4076:4067 4066 4065 4064 2079 2078 2077 129 2076:2067 2066 2065 2064 2063 2062 2061 128 2060:2051 2050 2049 2048 Subsector ...
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... Memory organization Table 13. Memory Map Sectors 127:64 Sector 2047 2046 2045 127 2044:2035 2034 2033 2032 2031 2030 2029 126 2028:2019 2018 2017 2016 1055 1054 1053 65 1052:1043 1042 1041 1040 1039 1038 1037 64 1036:1027 1026 1025 1024 52/157 Subsector 007F FFFFh ...
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... N25Q128 - 3 V Table 14. Memory Map Sectors 63:0 Sector 1023 1022 1021 63 1020:1011 1010 1009 1008 1007 1006 1005 62 1004:995 994 993 992 28: 12 Subsector 003F FFFFh 003F EFFFh 003F DFFFh 003F CFFFh 003F 2FFFh 003F 1FFFh 003F 0FFFh 003E FFFFh 003E EFFFh ...
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... Depending on the instruction, this might be followed by address bytes data bytes both or none. In XIP modes only read operation and exit XIP mode can be performed, and to read the memory content no instructions code are needed: the device directly receives addresses and after a configurable number of dummy clock cycles it outputs the required data. 9.1 ...
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... High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array are ignored during: – Write Status Register cycle – ...
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Instructions Table 15. Instruction set: extended SPI protocol (page Instruction Description RDID Read Identification READ Read Data Bytes FAST_READ Read Data Bytes at Higher Speed RDSFDP Read Serial Flash Discovery Parameter DOFR Dual Output Fast Read DIOFR ...
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... The manufacturer identification is assigned by JEDEC, and has the value 20h. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (BAh), and the memory capacity of the device in the second byte (18h). The UID is composed by 17 read only bytes, containing the length of the following data in the first byte ...
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... Serial Clock (C). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... Serial Clock (C). The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction ...
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Instructions Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence Instruction DQ0 High Impedance DQ1 ...
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... Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a configurable number of dummy clock cycles, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency Fc, during the falling edge of Serial Clock (C). ...
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... The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction. When the highest address is reached, the address counter rolls over to 00 0000h, so that the read sequence can be continued indefinitely ...
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... Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a configurable number of dummy clock cycles, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 ( maximum frequency fC, during the falling edge of Serial Clock (C) ...
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Instructions Figure 16. Quad Output Fast Read instruction sequence S Mode Mode 0 Instruction DQ0 Don’t Care DQ1 Don’t Care DQ2 DQ3 ‘1’ 9.1.8 Quad I/O Fast Read The Quad I/O Fast Read (QIOFR) ...
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... OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a configurable number of dummy clock cycles. Each bit is latched in on the rising edge of Serial Clock (C). Then the memory contents at that address are shifted out on Serial Data output (DQ1). Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock (C) ...
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Instructions 9.1.10 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Program or Erase, instructions: Page Program (PP), Dual Input Fast Program ...
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... DQ1 9.1.12 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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Instructions page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched ...
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N25Q128 - 3 V 9.1.13 Dual Input Fast Program (DIFP) The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) ...
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Instructions Figure 22. Dual Input Fast Program instruction sequence Instruction DQ0 DQ1 DQ0 DATA ...
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N25Q128 - 3 V Figure 23. Dual Input Extended Fast Program instruction sequence S Mode Mode 0 Instruction DQ0 DQ1 ...
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Instructions Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Quad Input Fast Program (QIFP) instruction is not executed. As soon as Chip Select (S) is driven ...
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... When bit 0 of byte 64 = '1', the 64 bytes of the OTP memory array can be programmed. When bit 0 of byte 64 = '0', the 64 bytes of the OTP memory array are read-only and cannot be programmed anymore. Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1 ...
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... Instructions Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the OTP memory array become read-only in a permanent way. Any Program OTP (POTP) instruction issued while an Erase or Program cycle is in progress is rejected without having any effect on the cycle that is in progress. A Program OTP cycle cannot be paused by a Program/Erase Suspend (PES) instruction ...
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N25Q128 - 3 V 9.1.18 Subsector Erase (SSE) The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the ...
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Instructions Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress ...
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N25Q128 - 3 V 9.1.21 Program/Erase Suspend The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular: Sector Erase, Subsector Erase, Page Program, Dual Input Page Program, Dual Input Extended Page program, Quad ...
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Instructions Table 20. Operations Allowed / Disallowed During Device States Device States and Sector (Same/Other) in Which Operation is Allowed/Disallowed (Yes/No) Standby State Program State Operation Sector Same Other Same All Reads except RDSR / Yes Yes RFSR Array Program: ...
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N25Q128 - 3 V 9.1.23 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register ...
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... If Write Protect (W/VPP) is driven Low not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has been set previously by a Write Enable (WREN) instruction. Therefore, all data bytes in the memory area that are software protected (SPM2) by the Block Protect (BP3, BP2, BP1, BP0) bits and the Top/Bottom (T/B) bit of the Status Register are also hardware protected against data modification ...
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... MSB Micron Technology, Inc., reserves the right to change products or specifications without notice. Memory content (1) Protected area Unprotected area Protected against PP, Ready to accept PP, DIFP, DIEFP, QIFP, DIFP, DIEFP, QIFP, QIEFP, SSE, SE and QIEFP, SSE, and SE BE instructions. instructions. PP, DIFP, DIEFP, ...
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... Lock Down bit it cannot be cleared to ‘0’, except by a power-up. b1 Down ‘0’ The Write Lock and Lock Down bits can be changed by writing new values to them. Program and Erase operations in this sector will not be executed. The memory ‘1’ contents will not be changed. Sector b0 ...
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N25Q128 - 3 V Table 23. Lock Register in Sector All sectors 1. Values of (b1, b0) after power-up are defined in 9.1.27 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to ...
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Instructions Figure 36. Clear Flag Status Register instruction sequence S C DQ0 DQ1 9.1.29 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. Figure 37. Read NV Configuration ...
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... The Write Non Volatile Configuration register (WRNVCR) instruction allows the user to change the values of all the Non Volatile Configuration Register bits. The Write Non Volatile Configuration Register impacts the memory behavior only after the next power on sequence. Figure 38. Write NV Configuration Register instruction sequence ...
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... The Write Volatile Configuration register (WRVCR) instruction allows the user to change the values of all the Volatile Configuration Register bits. The Write Volatile Configuration Register impacts the memory behavior right after the instruction is received by the device. Figure 40. Write Volatile Configuration Register instruction sequence ...
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N25Q128 - Instruction DQ0 High Impedance DQ1 Volatile Enhanced Configuration Register Out MSB ...
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... This Reset operation consists of two instructions: Reset Enable and Reset Memory. The Reset operation requires the Reset Enable instruction followed by the Reset Memory instruction. If the Reset Enable instruction is followed by any instruction other than Reset Memory disabled. Reset Memory is also disabled if the device is selected by driving chip select (S) and Clock (C) low. 88/157 1 ...
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... Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. All attempts to access the memory array during a Write Status Register cycle, a Write Non Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the internal Write Status Register cycle, Write Non Volatile Configuration Register, Program ...
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Instructions cycle or Erase cycle continues unaffected, the only exception is the Program/Erase Suspend instruction (PES), that can be used to pause all the program and the erase cycles but the Program OTP (POTP), Write Status Register (WRSR), Bulk Erase ...
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... The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in parallel on the 2 pins DQ0 and DQ1. After this, the 24-bit device identification, stored in the memory, will be shifted out on again in parallel on DQ1 and DQ0. Each two bits are shifted out during the falling edge of Serial Clock (C). ...
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... Dual Command Fast Read (DCFR) The Dual Command Fast Read (DCFR) instruction allows to read the memory in DIO-SPI protocol, parallelizing the instruction code, the address and the output data on two pins (DQ0 and DQ1). The Dual Command Fast Read (DCFR) instruction can be issued, when ...
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... N25Q128 - 3 V the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 0Bh, 3Bh or BBh, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI protocol. Except for the parallelizing on two pins of the instruction code, the Dual Command Fast Read instruction functionality is exactly the same as the Dual I/O Fast Read of the Extended SPI protocol ...
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Instructions 9.2.5 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as ...
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... The Dual Command Page Program (DCPP) instruction can be issued, when the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 02h, A2h or D2h, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI protocol ...
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... Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Except for the parallelizing of the instruction code, address and input data on the two pins DQ0 and DQ1, the instruction functionality (as well as the locking OTP method) is exactly the same as the Program OTP (POTP) instruction of the Extended SPI protocol ...
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N25Q128 - 3 V Figure 54. Subsector Erase instruction sequence DIO-SPI Instruction DQ0 DQ1 9.2.10 Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can ...
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Instructions Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Bulk Erase (BE) instruction of the Extended SPI protocol. Figure 56. Bulk Erase instruction sequence ...
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N25Q128 - 3 V 9.2.13 Program/Erase Resume After a Program/Erase suspend instruction, a Program/Erase Resume instruction is required to continue performing the suspended Program or Erase sequence. Except for the parallelizing of the instruction code on the two pins DQ0 ...
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Instructions is exactly the same as the Write Status Register (WRSR) instruction of the Extended SPI protocol. Figure 60. Write Status Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.16 Read Lock Register (RDLR) The Read Lock Register instruction is ...
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N25Q128 - 3 V Except for the parallelizing of the instruction code, the address and the input data on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write to Lock Register (WRLR) instruction ...
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Instructions Figure 64. Clear Flag Status Register instruction sequence DIO-SPI DQ0 DQ1 9.2.20 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. Figure 65. Read NV Configuration Register ...
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N25Q128 - 3 V Figure 66. Write NV Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.22 Read Volatile Configuration Register The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile Configuration Register to be read. Figure 67. Read ...
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Instructions Figure 68. Write Volatile Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.24 Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. Figure 69. Read Volatile ...
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... The Reset operation requires the Reset Enable instruction followed by the Reset Memory instruction. If the Reset Enable instruction is followed by any instruction other than Reset Memory disabled. Reset Memory is also disabled if the device is selected by driving chip select (S) and Clock (C) low. This instruction functions exactly as the Reset Enable instruction of the Extended SPI protocol, except that for this instruction the instruction code and input data are on two pins, DQ0 and DQ1 ...
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... Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. All attempts to access the memory array during a Write Status Register cycle, a Write Non Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the internal Write Status Register cycle, Write Non Volatile Configuration Register, Program ...
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N25Q128 - 3 V Table 26. Instruction set: QIO-SPI protocol Instruction Description MIORDID Multiple I/O read identification Read Serial Flash Discovery RDSFDP Parameter QCFR Quad Command Fast Read ROTP Read OTP (Read of OTP area) WREN Write Enable WRDI Write ...
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... DQ0, DQ1, DQ2 and DQ3. After this, the 24-bit device identification, stored in the memory, will be shifted out on again in parallel on DQ0, DQ1, DQ2 and DQ3. The identification bits are shifted out time during the falling edge of Serial Clock (C) ...
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N25Q128 - 3 V Figure 72. Multiple I/O Read Identification instruction and data-out sequence QIO- SPI S C AFh DQ0 DQ1 DQ2 DQ3 9.3.2 Read Serial Flash Discovery Parameter The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows reading the ...
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... DQ1, DQ2 and DQ3). The Quad Command Fast Read (QCFR) instruction can be issued, after the device is set in QIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 0Bh, 6Bh or EBh, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to QIO-SPI protocol ...
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N25Q128 - 3 V Figure 74. Quad Command Fast Read instruction and data-out sequence QIO-SPI, 0Bh S Mode Mode 0 Instruction 4 0 DQ0 DQ1 5 1 DQ2 6 2 DQ3 7 3 A23-16 ...
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Instructions Figure 76. Quad Command Fast Read instruction and data-out sequence QIO-SPI, EBh S Mode Mode 0 Instruction 4 0 DQ0 DQ1 5 1 DQ2 6 2 DQ3 7 3 A23-16 A15-8 A7-0 9.3.4 ...
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N25Q128 - 3 V Figure 77. Read OTP instruction and data-out sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.5 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Except for the ...
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... The Quad Command Page Program (QCPP) instruction can be issued, when the device is set in QIO-SPI mode, by sending to the memory indifferently one of the 3 instructions codes: 02h, 12h or 32h, the effect is exactly the same. The 3 instruction codes are all accepted to help the application code porting from Extended SPI protocol to QIO-SPI protocol ...
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... DQ0 DQ1 DQ2 DQ3 9.3.8 Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed 24-bit address Data In ...
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Instructions Except for the parallelizing of the instruction code, address and input data on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality (as well as the locking OTP method) is exactly the same as the Program OTP ...
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N25Q128 - 3 V Figure 84. Subsector Erase instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.10 Sector Erase (SE) The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it can be ...
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Instructions 9.3.11 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Except for the parallelizing of the instruction code on ...
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N25Q128 - 3 V Figure 87. Program/Erase Suspend instruction sequence QIO-SPI DQ0 DQ1 9.3.13 Program/Erase Resume After a Program/Erase suspend instruction, a Program/Erase Resume instruction is required to continue performing the suspended Program or Erase sequence. Except for the parallelizing ...
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Instructions 9.3.14 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. Except for the parallelizing of the instruction code and the output data on the four pins DQ0, DQ1, DQ2 and DQ3, ...
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N25Q128 - 3 V Figure 90. Write Status Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.16 Read Lock Register (RDLR) The Read Lock Register instruction is used to read the lock register content. Except for the parallelizing ...
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Instructions Figure 91. Read Lock Register instruction and data-out sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.17 Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock ...
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N25Q128 - 3 V Figure 92. Write to Lock Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.18 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. Except ...
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Instructions Figure 93. Read Flag Status Register instruction sequence QIO-SPI S Mode Mode 0 Instruction DQ0 DQ1 DQ2 DQ3 9.3.19 Clear Flag Status Register The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register ...
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N25Q128 - 3 V 9.3.20 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. Figure 95. Read NV Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 ...
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Instructions Figure 96. Write NV Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.22 Read Volatile Configuration Register The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile Configuration Register to be read. 126/157 ...
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N25Q128 - 3 V Figure 97. Read Volatile Configuration Register instruction sequence QIO-SPI S C Instruction DQ0 DQ1 DQ2 DQ3 9.3.23 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the ...
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Instructions 9.3.24 Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. Figure 99. Read Volatile Enhanced Configuration Register instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 ...
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N25Q128 - 3 V Figure 100. Write Volatile Enhanced Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 Volatile Enhanced Configuration Register In Instruction Micron Technology, ...
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... The Reset operation requires the Reset Enable instruction followed by the Reset Memory instruction. If the Reset Enable instruction is followed by any instruction other than Reset Memory disabled. Reset Memory is also disabled if the device is selected by driving chip select (S) and Clock (C) low. This instruction functions exactly as the Reset Enable instruction of the Extended SPI protocol, except that for this instruction the instruction code and input data are on four pins, DQ0, DQ1, DQ2 and DQ3 ...
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... While acting on the Non Volatile Configuration Register (bit 11 to bit 9, depending on which XIP type is required, single, dual or quad I/O) the memory enters in the selected XIP mode only after the next power-on sequence. The Non Volatile Configuration Register XIP configuration bits allows the memory to start directly in the required XIP mode (Single, Dual or Quad) after the power on ...
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XIP Operations Power On NVCR Check No Is XIP enabled ? Yes XIP mode No Yes XiP Confirmation bit = 0 ? 132/157 SPI standard mode (no VCR<3> XiP, VCR <3> Micron Technology, Inc., reserves ...
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... Register (WRNVCR) instruction. This instruction doesn't affect the XIP state until the next Power on sequence. In this case, after the next power on sequence, the memory directly accept addresses and then, after the dummy clock cycles (configurable), outputs the data as described here. For example to ...
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... DQ0 during the first dummy cycle after the address has been received), Then after the next de-select and select cycle (S pin set to 1 and then to 0) the memory codify the first 3 bytes received on the input pin(s) directly as an address, without any instruction code, and after the dummy clock cycles (configurable) directly outputs the data ...
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... XIP mode hold and exit The XIP mode does require at least one additional clock cycle to allow the XIP Confirmation bit to be sent to the memory on DQ0 during the first dummy clock cycle. The device decodes the XIP Confirmation bit with the scheme: ...
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... POR state and there is no issue. See In all the other cases possible to exit the memory from the XIP mode by sending the following rescue sequence at the first chip selection after a system reset: ...
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... Device does not respond to any instruction During a standard power-up phase, the device ignores all instructions but RDSR and RFSR; these instructions can be used to check the memory internal state according to power-up timing shown here. After power-up, the device is in the following state: ...
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Power-up and power-down Table 30. Power-up timing and V Symbol ( (min) to Read VTR CC ( (min) to device fully accessible VTW CC (1) V Write inhibit voltage WI 1. These parameters are characterized only. ...
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... Fast program/erase voltage V Electrostatic discharge voltage (human body model) ESD 1. Compliant with JEDEC Std. J-STD-020C (for small body, Sn- assembly), the Numonyx ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω 500 Ω). ...
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DC and AC parameters 14 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from ...
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N25Q128 - 3 V Table 35. DC Characteristics Symbol Parameter ILI Input leakage current ILO Output leakage current ICC1 Standby current Operating current (Fast Read Single I/O) ICC3 Operating current (Fast Read Dual I/O) Operating current (Fast Read Quad I/O) ...
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DC and AC parameters Note: The AC Characteristics data is preliminary. Table 36. AC Characteristics (page Symbol Alt. Clock frequency for the all the fC fC instructions (Extended SPI, DIO-SPI and QIO-SPI protocol) but the READ instruction ...
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N25Q128 - 3 V Table 36. AC Characteristics (page Symbol Alt. Enhanced program supply voltage High (6) tVPPHSL (VPPH) to Chip Select Low for Single and Dual I/O Page Program tW Write status register cycle time tCFSR ...
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DC and AC parameters Table 37. Reset Conditions Symbol Alt. Parameter (1)(2) tRLRH tRST Reset pulse width Reset Recovery (1) tRHSL tREC Time S# deselect to R (1) tSHRV valid Software reset tSHSL3 tREC1 recovery time 1. All values are ...
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N25Q128 - 3 V Figure 108. Serial input timing S tCHSL C tDVCH DQ0 DQ1 Figure 109. Write protect setup and hold timing during WRSR when SRWD=1 W/V PP tWHSL S C DQ0 DQ1 tSLCH tCHDX tCLCH MSB IN High ...
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DC and AC parameters Figure 110. Hold timing S C DQ1 DQ0 HOLD Figure 111. Output timing S C tCLQV tCLQX DQ1 ADDR. DQ0 LSB IN 146/157 tCHHL tHLQZ tCLQV tCLQX Micron Technology, Inc., reserves the right to change products ...
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N25Q128 - 3 V Figure 112. VPP S C DQ0 V PPH V PP timing H tVPPHSL Micron Technology, Inc., reserves the right to change products or specifications without notice. DC and AC parameters End of command (identified by WIP ...
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... Package mechanical 15 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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N25Q128 - 3 V Figure 114. VDFPN8 (MLP8) Very thin pitch Dual Flat Package No lead, 6 × 5 mm, package outline 0. Drawing is not to scale. 2. The ...
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Package mechanical Figure 115. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline SO-H 1. Drawing is not to scale. Table 40. SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data Symbol ...
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N25Q128 - 3 V Figure 116. SO8W – 8 lead plastic small outline, 208 mils body width, package outline 1. Drawing is not to scale. Table 41. SO8 wide – 8 lead plastic small outline, 208 mils body width, package ...
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Package mechanical Figure 117. TBGA - mm, 24-ball, mechanical package outline 1. Drawing is not to scale. 152/157 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All ...
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N25Q128 - 3 V Table 42. TBGA 6x8 mm 24-ball package dimensions MIN A A1 0.20 A2 Øb 0. balls aaa bbb ddd eee ...
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... Mbit Technology Feature set 1 = Byte addressability, Hold pin, Numonyx XiP 2 = Byte addressability, Hold pin, Basic XiP 3 = Byte addressability, Reset pin, Numonyx XiP 4 = Byte addressability, Reset pin, Basic XiP Operating voltage 3 = VCC = 2 3.6 V Block Structure E = Uniform subsector (4KB) and uniform sector (64KB) ...
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... N25Q128A13ESF40G Hold pin, Numonyx XiP N25Q128A13EF840E Byte addressability, N25Q128A13EF840F Hold pin, Numonyx XiP 1. Packing information details: E= tray, F= tape-n-reel, G= tube (16th digit of part number). 2. For further information on advanced security features, see your local Numonyx sales representative.. Block Features Structure Uniform TBGA24 Uniform ...
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Revision history 17 Revision history Table 45. Document revision history Date Revision 29-Jan.-2009 12-May.-2009 3-Sept-2009 10-Feb-2010 11-Oct-2010 17-Jan-2011 4-Feb-2011 156/157 1 Initial release. Added the TBGA ballout and package information; Made technical edits to the following sections: – Program/Erase Suspend ...
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N25Q128 - 3 V 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their ...