N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 79

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
9.1.23
9.1.24
S
C
DQ0
DQ1
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit (or the Program/Erase controller bit of the Flag Status
Register) before sending a new instruction to the device. It is also possible to read the
Status Register continuously, as shown here.
Figure 31. Read Status Register instruction sequence
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. After the write enable (WREN) instruction has been decoded and executed,
the device sets the write enable latch (WEL).
The write status register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on serial data input (DQ0). The write
status register (WRSR) instruction has no effect on b1 and b0 of the status register.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed write status register cycle (whose duration is tW) is
initiated. While the write status register cycle is in progress, the status register may still be
read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1
during the self-timed write status register cycle, and is 0 when it is completed. When the
cycle is completed, the write enable latch (WEL) is reset.
The write status register (WRSR) instruction allows the user to change the values of the
block protect (BP3, BP2, BP1, BP0) bits and the Top/Bottom (TP) bit, to define the size of
the area that is to be treated as read-only, as defined
(TB bit = 0)
(WRSR) instruction also allows the user to set and reset the status register write disable
(SRWD) bit in accordance with the Write Protect (W/VPP) signal. The status register write
disable (SRWD) bit and Write Protect (W/VPP) signal allow the device to be put in the
hardware protected mode (HPM). The write status register (WRSR) instruction is not
executed once the hardware protected mode (HPM) is entered.
0
High Impedance
1
2
Instruction
and
3
4
Table 11.: Protected area sizes, Lower (TB bit =
5
6
7
MSB
7
8
6
9 10 11 12 13 14 15
Status register out
5
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
2
1
0
Table 10.: Protected area sizes, Upper
MSB
7
6
Status register out
5
©2010 Micron Technology, Inc. All rights reserved.
1). The write status register
4
3
2
1
Instructions
0
7
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