CY7C1355B-100AC Cypress Semiconductor Corp, CY7C1355B-100AC Datasheet
CY7C1355B-100AC
Specifications of CY7C1355B-100AC
Available stocks
Related parts for CY7C1355B-100AC
CY7C1355B-100AC Summary of contents
Page 1
... Cypress Semiconductor Corporation Document #: 38-05117 Rev. *C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Functional Description The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the CY7C1355B/CY7C1357B is equipped with the advanced No ...
Page 2
... Logic Block Diagram – CY7C1355B (256K x 36) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN ADV/ ADDRESS A0, A1 REGISTER BW D MODE WE CE CLK C CEN OE CE1 CE2 CE3 ZZ ADV/ Logic Block Diagram – CY7C1357B (512K x 18) ADDRESS A0, A1 REGISTER MODE CE CLK C CEN OE CE1 CE2 ...
Page 3
... Pin Configurations DQP DDQ BYTE DDQ DNU DDQ BYTE DDQ DQP 30 D Document #: 38-05117 Rev. *C 100-lead TQFP CY7C1355B CY7C1355B CY7C1357B 80 DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP A Page ...
Page 4
... Pin Configurations (continued DDQ DDQ DNU BYTE DDQ DQP DDQ Document #: 38-05117 Rev. *C 100-lead TQFP CY7C1357B CY7C1355B CY7C1357B DDQ DQP DDQ BYTE DDQ DDQ Page ...
Page 5
... Pin Configurations (continued DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ 72M U V DDQ Document #: 38-05117 Rev. *C 119-ball BGA (3 Chip Enables with JTAG) CY7C1355B (256K x 36 18M CE A ADV/ DQP CLK CEN DQP MODE 72M A A TMS TDI TCK CY7C1357B (512K x 18) ...
Page 6
... V D DDQ 72M A R MODE NC / 36M 288M CE2 DDQ DDQ DDQ DDQ DDQ / DDQ DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05117 Rev. *C 165-ball fBGA (3 Chip enable with JTAG) CY7C1355B (256K x 36 CLK TDI TMS CY7C1357B (512K x 18 ...
Page 7
... CY7C1355B–Pin Definitions Name TQFP BGA 37,36,32,33, P4,N4,A2 34,35,44,45, C2,R2,A3, 46,47,48,49, B3,C3,T3, 50,81,82,83, G4,T4,A5, 99,100 B5,C5,T5, A6,C6,R6 93,94,95,96 L5,G5,G3 ADV/LD CLK CEN Document #: 38-05117 Rev. *C fBGA I/O R6,P6,A2, Input- Address Inputs used to select one of the 256K A9,A10,B2, Synchronous address locations. Sampled at the rising edge of the B10,P3,P4, CLK ...
Page 8
... CY7C1355B–Pin Definitions Name TQFP BGA 52,53,56,57, K6,L6,M6 58,59,62,63, N6,K7,L7, 68,69,72,73, N7,P7,E6, 74,75,78,79, F6,G6,H6, 2,3,6,7,8,9, D7,E7,G7, 12,13,18,19, H7,D1,E1, 22,23,24,25, G1,H1,E2, 28,29 F2,G2,H2, K1,L1,N1, P1,K2,L2, M2,N2 51,80,1,30 P6,D6,D2, DQP [A:D] P2 MODE 15,41,65,91 J2,C4,J4, DD R4,J6 V 4,11,20,27, A1,F1,J1, DDQ 54,61,70,77 M1,U1, A7,F7,J7, M7,U7 V 5,10,17,21, ...
Page 9
... CY7C1355B–Pin Definitions Name TQFP BGA TCK - U4 NC 16,38,39,42, B1,C1,R1, 43,66,84 T1,T2,J3, A4,D4,L4, J5,R5,T6, U6,B7,C7 /DNU CY7C1357B–Pin Definitions Name TQFP BGA 37,36,32,33, P4,N4,A2 34,35,44,45, C2,R2,T2, 46,47,48,49, A3,B3,C3, 50,80,81,82, T3,A5,B5, 83,99,100 C5,T5,A6, C6,R6,T6 93,94 G3, ADV/LD CLK Document #: 38-05117 Rev. *C (continued) fBGA ...
Page 10
... Serial data-out to the JTAG circuit. Delivers data on the output negative edge of TCK. If the JTAG feature is not being Synchronous utilized, this pin should be left unconnected. This pin is not available on TQFP packages. CY7C1355B CY7C1357B Description are placed in a three-state condition. The [A:B] . During Write sequences, ...
Page 11
... C1,C2,C10, pins and are not internally connected to the die. D1,D10,E1, E10,F1,F10, G1,G10,H1, H3,H9,H10, J2,J11,K2, K11,L2,L11, M2,M11,N2, N5,N6,N7, N10,N11,P1, P2,P11,R2 - Ground/DNU This pin can be connected to Ground or should be left floating. CY7C1355B CY7C1357B Description through a pull DD . This pin This SS Page ...
Page 12
... A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple Byte Write operations. Because the CY7C1355B/CY7C1357B is a common I device, data should not be driven into the device while the 1 2 outputs are active ...
Page 13
... CE ZZ ADV/ data when OE is active. X CY7C1355B CY7C1357B Second Third Address Address A1 Min. Max CYC 2t CYC 2t CYC 0 CEN CLK L->H Three-State L->H Three-State L->H Three-State L->H Three-State L->H Data Out ( L->H Data Out ( L->H Three-State L->H Three-State L->H Data In (D) X ...
Page 14
... Truth Table for Read/Write Function (CY7C1355B) Read Write No bytes written Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Byte C – (DQ and DQP ) C C Write Byte D – (DQ and DQP ) D D Write All Bytes Truth Table for Read/Write ...
Page 15
... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1355B/CY7C1357B incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
Page 16
... TAP controller’s capture set-up plus hold time (t The SRAM clock input might not be captured correctly if there PRELOAD portion way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1355B CY7C1357B instructions. Unlike the SAMPLE/PRELOAD plus t ). ...
Page 17
... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE [9, 10] Over the operating Range Description / ns CY7C1355B CY7C1357B TDOV t TDOX UNDEFINED Min. Max Page ...
Page 18
... DDQ DDQ DDQ I = 100 µ DDQ V DDQ V DDQ V DDQ V DDQ V DDQ GND < V < DDQ CY7C1355B CY7C1357B 1.25V 50 TDO 20pF O Min. Max. = 3.3V 2.4 = 2.5V 2.0 = 3.3V 2.9 = 2.5V 2.1 = 3.3V 0.4 = 2.5V 0.4 = 3.3V 0.2 = 2.5V 0.2 = 3. ...
Page 19
... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1355B CY7C1357B Description Describes the version number Reserved for Internal Use ...
Page 20
... BGA Boundary Scan Order CY7C1355B (256K x 36) BIT BALL Signal BIT # ID Name # 1 CLK CEN ADV/ DQP DQP Document #: 38-05117 Rev. *C BALL Signal BIT# BALL ID ID Name MODE 5 P2 DQP Internal Internal Internal Internal Internal Internal C D2 DQP 24 Internal Internal Internal ...
Page 21
... Boundary Scan Order CY7C1355B (256K x 36) BIT# BALL Signal BIT# ID Name 1 B6 CLK CEN ADV/ B10 A10 C11 DQP E10 F10 G10 D10 D11 E11 F11 G11 H11 J10 K10 L10 M10 J11 K11 L11 M11 N11 DQP R11 ...
Page 22
... DD IN 0.3V 0, inputs static /2), undershoot: V (AC) > –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < CY7C1355B CY7C1357B Ambient Temperature V DD 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% -40°C to +85°C Min. Max. 3.135 3.63 3.135 ...
Page 23
... Test Conditions T = 25° MHz 3.3V 2.5V DDQ R = 317Ω 3.3V OUTPUT 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V OUTPUT =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1355B CY7C1357B TQFP BGA fBGA Package Package Package TQFP BGA fBGA Package Package Package ...
Page 24
... DDQ is the time that the power needs to be supplied above V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1355B CY7C1357B 117 MHz 100 MHz Min. Max. Min. Max 8 ...
Page 25
... CYC CDV t DOH t CLZ D(A2) Q(A3) D(A2+1) t OEHZ BURST READ READ WRITE Q(A3) Q(A4) D(A2+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1355B CY7C1357B OEV t CHZ Q(A4) Q(A4+1) D(A5) Q(A6) t DOH t OELZ BURST WRITE READ WRITE READ D(A5) Q(A6) ...
Page 26
... CDV t DOH t CLZ D(A2) Q(A3) Q(A4) D(A2+1) t OEHZ BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED CY7C1355B CY7C1357B OEV t CHZ Q(A4+1) D(A5) Q(A6) t DOH t OELZ WRITE READ WRITE D(A5) Q(A6) D(A7) 10 D(A7) DESELECT Page ...
Page 27
... CY7C1357B-133BGI CY7C1355B-133BZC CY7C1357B-133BZC CY7C1355B-133BZI CY7C1357B-133BZI 117 CY7C1355B-117AC CY7C1357B-117AC CY7C1355B-117AI CY7C1357B-117AI CY7C1355B-117BGC CY7C1357B-117BGC CY7C1355B-117BGI CY7C1357B-117BGI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Notes: 25. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. ...
Page 28
... Ordering Information (continued) Speed (MHz) Ordering Code CY7C1355B-117BZC CY7C1357B-117BZC CY7C1355B-117BZI CY7C1357B-117BZI 100 CY7C1355B-100AC CY7C1357B-100AC CY7C1355B-100AI CY7C1357B-100AI CY7C1355B-100BGC CY7C1357B-100BGC CY7C1355B-100BGI CY7C1357B-100BGI CY7C1355B-100BZC CY7C1357B-100BZC CY7C1355B-100BZI CY7C1357B-100BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05117 Rev. *C ...
Page 29
... Package Diagrams 100-pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05117 Rev. *C CY7C1355B CY7C1357B 51-85050-*A Page ...
Page 30
... Package Diagrams (continued) Document #: 38-05117 Rev. *C 119-Lead PBGA ( 2.4 mm) BG119 CY7C1355B CY7C1357B 51-85115-*B Page ...
Page 31
... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1355B CY7C1357B 51-85122-*C ...
Page 32
... Document History Page Document Title: CY7C1355B/CY7C1357B 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05117 REV. ECN NO. Issue Date ** 117908 08/28/02 *A 123161 12/18/02 *B 200980 See ECN *C 239272 See ECN Document #: 38-05117 Rev. *C Orig. of Change RCS New Data Sheet RCS Removed Preliminary Statue (all pages) ...