M48Z128-70PM1 STMicroelectronics, M48Z128-70PM1 Datasheet

IC NVSRAM 1MBIT 70NS 32DIP

M48Z128-70PM1

Manufacturer Part Number
M48Z128-70PM1
Description
IC NVSRAM 1MBIT 70NS 32DIP
Manufacturer
STMicroelectronics
Datasheets

Specifications of M48Z128-70PM1

Format - Memory
RAM
Memory Type
NVSRAM (Non-Volatile SRAM)
Memory Size
1M (128K x 8)
Speed
70ns
Interface
Parallel
Voltage - Supply
4.75 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
32-DIP (600 mil) Module
Data Bus Width
8 bit
Organization
128 Kb x 8
Interface Type
Parallel
Access Time
70 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.75 V
Operating Current
105 mA
Maximum Operating Temperature
70 C
Minimum Operating Temperature
0 C
Mounting Style
Through Hole
Memory Configuration
128K X 8
Nvram Features
Internal Battery
Supply Voltage Range
4.5V To 5.5V
Memory Case Style
DIP
No. Of Pins
32
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2873-5
FEATURES SUMMARY
February 2005
* Contact local ST sales office for availability.
INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, AND
BATTERY
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
BATTERY INTERNALLY ISOLATED UNTIL
POWER IS FIRST APPLIED
AUTOMATIC POWER-FAIL CHIP
DESELECT and WRITE PROTECTION
WRITE PROTECT VOLTAGES:
(V
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY
SNAPHAT HOUSING (BATTERY) IS
REPLACEABLE
PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
EQUIVALENT SURFACE-MOUNT (SMT)
SOLUTION REQUIRES A 28-PIN M40Z300/
W and A STAND-ALONE 128K x8 LPSRAM
(SNAPHAT
PFD
5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER
M48Z128: V
4.5V
M48Z128Y: V
4.2V
M48Z128V: V
2.8V
= Power-fail Deselect Voltage)
V
V
V
®
PFD
PFD
PFD
Top to be ordered separately)
CC
CC
CC
4.75V
4.5V
3.0V
= 4.75 to 5.5V
= 4.5 to 5.5V
= 3.0 to 3.6V
Figure 1. 32-pin PMDIP Module
M48Z128Y, M48Z128V*
32
PMDIP32 (PM)
1
Module
M48Z128
®
SRAM
1/21

Related parts for M48Z128-70PM1

M48Z128-70PM1 Summary of contents

Page 1

... JEDEC STANDARD 128K x 8 SRAMs EQUIVALENT SURFACE-MOUNT (SMT) SOLUTION REQUIRES A 28-PIN M40Z300/ W and A STAND-ALONE 128K x8 LPSRAM ® (SNAPHAT Top to be ordered separately) * Contact local ST sales office for availability. February 2005 M48Z128Y, M48Z128V* Figure 1. 32-pin PMDIP Module 32 1 PMDIP32 (PM) Module M48Z128 ® SRAM ...

Page 2

... M48Z128, M48Z128Y, M48Z128V* 2/21 ...

Page 3

... Figure 16.SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline . . . . . . . . . . . . . . 18 Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data . . . . . . 18 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 REVISION HISTORY Table 18. Revision History M48Z128, M48Z128Y, M48Z128V* 3/21 ...

Page 4

... DIP module. This solution is available in two special packages to provide a highly integrated battery backed-up memory solution. The M48Z128/Y non-volatile pin and func- tion equivalent to any JEDEC standard 128K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility ...

Page 5

... A16 2 31 A14 3 30 A12 M48Z128 M48Z128Y M48Z128V DQ0 13 20 DQ1 14 19 DQ2 AI01195 V CC POWER SRAM ARRAY AND E INTERNAL BATTERY M48Z128, M48Z128Y, M48Z128V A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 A0-A16 DQ0-DQ7 131,072 AI01196 5/21 ...

Page 6

... NVRAM M48Z128 M48Z128Y M48Z128V Note: 1. Connection of Threshold Select Pin (Pin 13) of SUPERVISOR (M40Z300/300W). 6/21 OUT CON CON CON CON RST BL V 4.5V (M48Z128Y) or connect THS pin to V PFD V 3.0V (M48Z128V). PFD LPSRAM SUPERVISOR 5V 1Mb LPSRAM 5V 1Mb LPSRAM 3V 1Mb LPSRAM 1Mb LPSRAM ...

Page 7

... OPERATING MODES The M48Z128/Y/V also has its own Power-fail De- tect circuit. The control circuitry constantly moni- tors the single V supply for an out of tolerance CC condition. When V is out of tolerance, the circuit CC write protects the SRAM, providing a high degree Table 3. Operating Modes Mode ...

Page 8

... M48Z128, M48Z128Y, M48Z128V* Figure 7. Address Controlled, READ Mode AC Waveforms A0-A16 DQ0-DQ7 Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High. Table 4. READ Mode AC Characteristics Symbol Parameter t READ Cycle Time AVAV t Address Valid to Output Valid AVQV t Chip Enable Low to Output Valid ...

Page 9

... WRITE Mode The M48Z128/Y the WRITE Mode whenev and E are active. The start of a WRITE is ref- erenced from the latter occurring falling edge WRITE is terminated by the earlier rising edge The addresses must be held valid throughout the cycle must return high for minimum of ...

Page 10

... M48Z128, M48Z128Y, M48Z128V* Table 5. WRITE Mode AC Characteristics Symbol Parameter t WRITE Cycle Time AVAV t Address Valid to WRITE Enable Low AVWL t Address Valid to Chip Enable Low AVEL t WRITE Enable Pulse Width WLWH t Chip Enable Low to Chip Enable High ELEH t WRITE Enable High to Address Transition ...

Page 11

... When V WP below V , the control circuit switches power to SO the internal energy source which preserves data. The internal coin cell will maintain data in the M48Z128/Y/V after the initial application accumulated period of at least 10 years when V is less than system power returns CC SO ...

Page 12

... M48Z128, M48Z128Y, M48Z128V* MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicat the Operating sections of this specification is Table 6 ...

Page 13

... Table 8. Capacitance Symbol Parameter C Input Capacitance IN (3) Input / Output Capacitance C IO Note: 1. Effective capacitance measured with power supply at 5V (M48Z128/Y) or 3.3V (M48Z128V); sampled only, not 100% tested 25° 1MHz. 3. Outputs deselected. Table 9. DC Characteristics Sym Parameter I Input Leakage Current LI (2) Output Leakage Current ...

Page 14

... M48Z128, M48Z128Y, M48Z128V* Figure 12. Power Down/Up Mode AC Waveforms PFD (max) V PFD (min tWP E RECOGNIZED OUTPUTS VALID (PER CONTROL INPUT) Table 10. Power Down/Up AC Characteristics Symbol (2) V (max PFD PFD F (3) V (min PFD (min PFD PFD (min PFD t Write Protect Time Recovery Time ER Note: 1 ...

Page 15

... M48Z128, M48Z128Y, M48Z128V PMDIP inches Typ Min 0.365 0.375 0.015 0.017 0.023 0.008 0.013 1.670 1.700 0.710 0.740 0.090 0.110 1.350 1 ...

Page 16

... M48Z128, M48Z128Y, M48Z128V* Figure 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline SOH-A Note: Drawing is not to scale. Table 13. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data Symbol Typ 1. 16/ Min Max 3.05 0.05 0.36 2.34 2.69 ...

Page 17

... E mm Min Max 9.78 6.73 7.24 6.48 6.99 0.38 0.46 0.56 21.21 21.84 14.22 14.99 15.55 15.95 3.20 3.61 2.03 2.29 M48Z128, M48Z128Y, M48Z128V SHZP-A inches Typ Min 0.385 0.265 0.285 0.255 0.275 0.015 0.018 0.022 0.835 0.860 0.560 0.590 0.612 ...

Page 18

... M48Z128, M48Z128Y, M48Z128V* Figure 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data Symb Typ 18/ Min Max 10.54 8.00 8.51 7.24 8.00 0.38 0.46 ...

Page 19

... V = 3.0 to 3.6V PFD Speed –70 = 70ns (for M48Z128/Y) –85 = 85ns (for M48Z128/Y/V) –120 = 120ns (for M48Z128/Y/V) (2) Package PM = PMDIP32 Temperature Range 70°C Note: 1. Contact Local Sales Office 2. The SOIC package (SOH28) requires the battery package (SNAPHAT “M4Zxx-BR00SH” in plastic tube or “M4Zxx-BR00SHTR” in Tape & Reel form. ...

Page 20

... M48Z128, M48Z128Y, M48Z128V* REVISION HISTORY Table 18. Revision History Date Version May 1999 1.0 First Issue 13-Apr-00 2.0 Document Layout changed; surface-Mount Chip Set solution added t changed (Table 4) 20-Jun-00 2.1 GLQX 19-Jul-00 2.2 M48Z128V added 14-Sep-01 3.0 Reformatted; added temperature information (Table 10, 11) 07-Nov-01 3 ...

Page 21

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