M48Z128Y-70PM1 STMicroelectronics, M48Z128Y-70PM1 Datasheet - Page 7

• Manufacturer Part Number: M48Z128Y-70PM1
• Description: IC NVSRAM 1MBIT 70NS 32DIP
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48Z128Y-70PM1

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-DIP (600 mil) Module
• Data Bus Width: 8 bit
• Organization: 128 Kb x 8
• Interface Type: Parallel
• Access Time: 70 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Operating Current: 105 mA
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Word Size: 8b
• Density: 1Mb
• Access Time (max): 70ns
• Operating Supply Voltage (typ): 5V
• Package Type: PMDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Through Hole
• Supply Current: 105mA
• Memory Configuration: 128K X 8
• Nvram Features: Internal Battery
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: PMDIP
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2874-5

OPERATING MODES
The M48Z128/Y/V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single V
condition. When V
write protects the SRAM, providing a high degree
Table 3. Operating Modes
Note: X = V
READ Mode
The M48Z128/Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 1,048,576 locations in
the static storage array. Thus, the unique address
specified by the 17 address inputs defines which
one of the 131,072 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
address input signal is stable, providing that the E
and G (Output Enable) access times are also sat-
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
Deselect
WRITE
READ
READ
Deselect
Deselect
V
Mode
1. See
IH
G
DQ0-DQ7
Table 11., page 14
or V
IL
; V
CC
V
SO
CC
SO
= Battery Back-up Switchover Voltage.
supply for an out of tolerance
4.75 to 5.5V
is out of tolerance, the circuit
4.5 to 5.5V
3.0 to 3.6V
to V
V
PFD
or
or
for details.
SO
CC
(1)
(min)
AVQV
(1)
) after the last
tAVQV
tGLQV
E
V
V
V
V
E
X
X
IH
IL
IL
IL
tAVAV
VALID
V
V
G
X
X
X
X
IH
of data security in the midst of unpredictable sys-
tem operation brought on by low V
below the switchover voltage (V
cuitry connects the battery which maintains data
until valid power returns.
IL
isfied. If the E and G access times are not met, val-
id data will be available after the later of Chip
Enable Access time (t
cess Time (t
state Data I/O signals is controlled by E and G. If
the outputs are activated before t
lines will be driven to an indeterminate state until
t
and G remain low, output data will remain valid for
Output Data Hold time (t
minate until the next Address Access.
AVQV
. If the address inputs are changed while E
V
V
V
W
X
X
X
IH
IH
IL
M48Z128, M48Z128Y, M48Z128V*
GLQV
tAXQX
DQ0-DQ7
High Z
High Z
High Z
High Z
). The state of the eight three-
D
D
OUT
IN
ELQV
AXQX
) or Output Enable Ac-
Battery Back-up Mode
) but will go indeter-
CMOS Standby
SO
), the control cir-
CC
Standby
AVQV
AI01197
Power
Active
Active
Active
. As V
, the data
CC
falls
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